mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-25 05:34:00 +08:00
f150abe101
Pull ARM-v7M support from Uwe Kleine-König:
"All but the last patch were in next since next-20130418 without issues.
The last patch fixes a problem in combination with
8164f7a (ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 register)
which triggers a WARN_ON without an implemented read_cpuid_ext.
The branch merges fine into v3.10-rc1 and I'd be happy if you pulled it
for 3.11-rc1. The only missing piece to be able to run a Cortex-M3 is
the irqchip driver that will go in via Thomas Gleixner and platform
specific stuff."
366 lines
9.2 KiB
ArmAsm
366 lines
9.2 KiB
ArmAsm
#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/errno.h>
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#include <asm/thread_info.h>
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#include <asm/v7m.h>
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@ Bad Abort numbers
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@ -----------------
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@
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#define BAD_PREFETCH 0
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#define BAD_DATA 1
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#define BAD_ADDREXCPTN 2
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#define BAD_IRQ 3
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#define BAD_UNDEFINSTR 4
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@
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@ Most of the stack format comes from struct pt_regs, but with
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@ the addition of 8 bytes for storing syscall args 5 and 6.
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@ This _must_ remain a multiple of 8 for EABI.
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@
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#define S_OFF 8
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/*
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* The SWI code relies on the fact that R0 is at the bottom of the stack
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* (due to slow/fast restore user regs).
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*/
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#if S_R0 != 0
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#error "Please fix"
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#endif
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.macro zero_fp
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#ifdef CONFIG_FRAME_POINTER
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mov fp, #0
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#endif
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.endm
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.macro alignment_trap, rtemp
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#ifdef CONFIG_ALIGNMENT_TRAP
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ldr \rtemp, .LCcralign
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ldr \rtemp, [\rtemp]
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mcr p15, 0, \rtemp, c1, c0
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#endif
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.endm
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#ifdef CONFIG_CPU_V7M
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/*
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* ARMv7-M exception entry/exit macros.
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*
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* xPSR, ReturnAddress(), LR (R14), R12, R3, R2, R1, and R0 are
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* automatically saved on the current stack (32 words) before
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* switching to the exception stack (SP_main).
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*
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* If exception is taken while in user mode, SP_main is
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* empty. Otherwise, SP_main is aligned to 64 bit automatically
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* (CCR.STKALIGN set).
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*
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* Linux assumes that the interrupts are disabled when entering an
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* exception handler and it may BUG if this is not the case. Interrupts
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* are disabled during entry and reenabled in the exit macro.
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*
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* v7m_exception_slow_exit is used when returning from SVC or PendSV.
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* When returning to kernel mode, we don't return from exception.
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*/
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.macro v7m_exception_entry
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@ determine the location of the registers saved by the core during
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@ exception entry. Depending on the mode the cpu was in when the
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@ exception happend that is either on the main or the process stack.
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@ Bit 2 of EXC_RETURN stored in the lr register specifies which stack
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@ was used.
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tst lr, #EXC_RET_STACK_MASK
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mrsne r12, psp
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moveq r12, sp
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@ we cannot rely on r0-r3 and r12 matching the value saved in the
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@ exception frame because of tail-chaining. So these have to be
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@ reloaded.
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ldmia r12!, {r0-r3}
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@ Linux expects to have irqs off. Do it here before taking stack space
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cpsid i
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sub sp, #S_FRAME_SIZE-S_IP
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stmdb sp!, {r0-r11}
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@ load saved r12, lr, return address and xPSR.
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@ r0-r7 are used for signals and never touched from now on. Clobbering
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@ r8-r12 is OK.
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mov r9, r12
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ldmia r9!, {r8, r10-r12}
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@ calculate the original stack pointer value.
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@ r9 currently points to the memory location just above the auto saved
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@ xPSR.
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@ The cpu might automatically 8-byte align the stack. Bit 9
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@ of the saved xPSR specifies if stack aligning took place. In this case
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@ another 32-bit value is included in the stack.
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tst r12, V7M_xPSR_FRAMEPTRALIGN
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addne r9, r9, #4
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@ store saved r12 using str to have a register to hold the base for stm
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str r8, [sp, #S_IP]
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add r8, sp, #S_SP
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@ store r13-r15, xPSR
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stmia r8!, {r9-r12}
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@ store old_r0
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str r0, [r8]
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.endm
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/*
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* PENDSV and SVCALL are configured to have the same exception
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* priorities. As a kernel thread runs at SVCALL execution priority it
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* can never be preempted and so we will never have to return to a
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* kernel thread here.
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*/
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.macro v7m_exception_slow_exit ret_r0
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cpsid i
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ldr lr, =EXC_RET_THREADMODE_PROCESSSTACK
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@ read original r12, sp, lr, pc and xPSR
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add r12, sp, #S_IP
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ldmia r12, {r1-r5}
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@ an exception frame is always 8-byte aligned. To tell the hardware if
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@ the sp to be restored is aligned or not set bit 9 of the saved xPSR
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@ accordingly.
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tst r2, #4
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subne r2, r2, #4
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orrne r5, V7M_xPSR_FRAMEPTRALIGN
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biceq r5, V7M_xPSR_FRAMEPTRALIGN
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@ write basic exception frame
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stmdb r2!, {r1, r3-r5}
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ldmia sp, {r1, r3-r5}
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.if \ret_r0
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stmdb r2!, {r0, r3-r5}
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.else
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stmdb r2!, {r1, r3-r5}
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.endif
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@ restore process sp
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msr psp, r2
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@ restore original r4-r11
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ldmia sp!, {r0-r11}
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@ restore main sp
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add sp, sp, #S_FRAME_SIZE-S_IP
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cpsie i
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bx lr
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.endm
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#endif /* CONFIG_CPU_V7M */
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@
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@ Store/load the USER SP and LR registers by switching to the SYS
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@ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not
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@ available. Should only be called from SVC mode
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@
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.macro store_user_sp_lr, rd, rtemp, offset = 0
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mrs \rtemp, cpsr
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eor \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
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msr cpsr_c, \rtemp @ switch to the SYS mode
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str sp, [\rd, #\offset] @ save sp_usr
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str lr, [\rd, #\offset + 4] @ save lr_usr
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eor \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
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msr cpsr_c, \rtemp @ switch back to the SVC mode
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.endm
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.macro load_user_sp_lr, rd, rtemp, offset = 0
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mrs \rtemp, cpsr
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eor \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
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msr cpsr_c, \rtemp @ switch to the SYS mode
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ldr sp, [\rd, #\offset] @ load sp_usr
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ldr lr, [\rd, #\offset + 4] @ load lr_usr
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eor \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
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msr cpsr_c, \rtemp @ switch back to the SVC mode
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.endm
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#ifndef CONFIG_THUMB2_KERNEL
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.macro svc_exit, rpsr, irq = 0
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.if \irq != 0
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@ IRQs already off
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#ifdef CONFIG_TRACE_IRQFLAGS
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@ The parent context IRQs must have been enabled to get here in
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@ the first place, so there's no point checking the PSR I bit.
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bl trace_hardirqs_on
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#endif
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.else
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@ IRQs off again before pulling preserved data off the stack
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disable_irq_notrace
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#ifdef CONFIG_TRACE_IRQFLAGS
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tst \rpsr, #PSR_I_BIT
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bleq trace_hardirqs_on
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tst \rpsr, #PSR_I_BIT
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blne trace_hardirqs_off
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#endif
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.endif
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msr spsr_cxsf, \rpsr
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#if defined(CONFIG_CPU_V6)
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ldr r0, [sp]
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strex r1, r2, [sp] @ clear the exclusive monitor
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ldmib sp, {r1 - pc}^ @ load r1 - pc, cpsr
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#elif defined(CONFIG_CPU_32v6K)
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clrex @ clear the exclusive monitor
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ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
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#else
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ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
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#endif
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.endm
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.macro restore_user_regs, fast = 0, offset = 0
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ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
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ldr lr, [sp, #\offset + S_PC]! @ get pc
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msr spsr_cxsf, r1 @ save in spsr_svc
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#if defined(CONFIG_CPU_V6)
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strex r1, r2, [sp] @ clear the exclusive monitor
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#elif defined(CONFIG_CPU_32v6K)
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clrex @ clear the exclusive monitor
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#endif
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.if \fast
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ldmdb sp, {r1 - lr}^ @ get calling r1 - lr
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.else
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ldmdb sp, {r0 - lr}^ @ get calling r0 - lr
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.endif
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mov r0, r0 @ ARMv5T and earlier require a nop
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@ after ldm {}^
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add sp, sp, #S_FRAME_SIZE - S_PC
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movs pc, lr @ return & move spsr_svc into cpsr
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.endm
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.macro get_thread_info, rd
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mov \rd, sp, lsr #13
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mov \rd, \rd, lsl #13
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.endm
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@
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@ 32-bit wide "mov pc, reg"
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@
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.macro movw_pc, reg
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mov pc, \reg
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.endm
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#else /* CONFIG_THUMB2_KERNEL */
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.macro svc_exit, rpsr, irq = 0
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.if \irq != 0
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@ IRQs already off
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#ifdef CONFIG_TRACE_IRQFLAGS
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@ The parent context IRQs must have been enabled to get here in
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@ the first place, so there's no point checking the PSR I bit.
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bl trace_hardirqs_on
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#endif
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.else
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@ IRQs off again before pulling preserved data off the stack
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disable_irq_notrace
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#ifdef CONFIG_TRACE_IRQFLAGS
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tst \rpsr, #PSR_I_BIT
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bleq trace_hardirqs_on
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tst \rpsr, #PSR_I_BIT
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blne trace_hardirqs_off
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#endif
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.endif
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ldr lr, [sp, #S_SP] @ top of the stack
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ldrd r0, r1, [sp, #S_LR] @ calling lr and pc
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clrex @ clear the exclusive monitor
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stmdb lr!, {r0, r1, \rpsr} @ calling lr and rfe context
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ldmia sp, {r0 - r12}
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mov sp, lr
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ldr lr, [sp], #4
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rfeia sp!
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.endm
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#ifdef CONFIG_CPU_V7M
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/*
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* Note we don't need to do clrex here as clearing the local monitor is
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* part of each exception entry and exit sequence.
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*/
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.macro restore_user_regs, fast = 0, offset = 0
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.if \offset
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add sp, #\offset
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.endif
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v7m_exception_slow_exit ret_r0 = \fast
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.endm
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#else /* ifdef CONFIG_CPU_V7M */
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.macro restore_user_regs, fast = 0, offset = 0
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clrex @ clear the exclusive monitor
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mov r2, sp
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load_user_sp_lr r2, r3, \offset + S_SP @ calling sp, lr
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ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
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ldr lr, [sp, #\offset + S_PC] @ get pc
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add sp, sp, #\offset + S_SP
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msr spsr_cxsf, r1 @ save in spsr_svc
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.if \fast
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ldmdb sp, {r1 - r12} @ get calling r1 - r12
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.else
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ldmdb sp, {r0 - r12} @ get calling r0 - r12
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.endif
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add sp, sp, #S_FRAME_SIZE - S_SP
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movs pc, lr @ return & move spsr_svc into cpsr
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.endm
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#endif /* ifdef CONFIG_CPU_V7M / else */
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.macro get_thread_info, rd
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mov \rd, sp
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lsr \rd, \rd, #13
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mov \rd, \rd, lsl #13
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.endm
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@
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@ 32-bit wide "mov pc, reg"
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@
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.macro movw_pc, reg
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mov pc, \reg
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nop
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.endm
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#endif /* !CONFIG_THUMB2_KERNEL */
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/*
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* Context tracking subsystem. Used to instrument transitions
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* between user and kernel mode.
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*/
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.macro ct_user_exit, save = 1
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#ifdef CONFIG_CONTEXT_TRACKING
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.if \save
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stmdb sp!, {r0-r3, ip, lr}
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bl user_exit
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ldmia sp!, {r0-r3, ip, lr}
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.else
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bl user_exit
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.endif
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#endif
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.endm
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.macro ct_user_enter, save = 1
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#ifdef CONFIG_CONTEXT_TRACKING
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.if \save
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stmdb sp!, {r0-r3, ip, lr}
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bl user_enter
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ldmia sp!, {r0-r3, ip, lr}
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.else
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bl user_enter
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.endif
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#endif
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.endm
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/*
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* These are the registers used in the syscall handler, and allow us to
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* have in theory up to 7 arguments to a function - r0 to r6.
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*
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* r7 is reserved for the system call number for thumb mode.
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*
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* Note that tbl == why is intentional.
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*
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* We must set at least "tsk" and "why" when calling ret_with_reschedule.
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*/
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scno .req r7 @ syscall number
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tbl .req r8 @ syscall table pointer
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why .req r8 @ Linux syscall (!= 0)
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tsk .req r9 @ current thread_info
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