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ef37d337e1
Instead of having the SoC code in arch/arm/mach-mvebu/platsmp.c do the set_smp_cross_call() to register the IPI-triggering function, it makes more sense to do exactly what the GIC driver is doing: let the irqchip driver do it. This way, it avoids having to expose the armada_mpic_send_doorbell() function between the irqchip driver and the SoC code. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397483648-26611-5-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
131 lines
3.2 KiB
C
131 lines
3.2 KiB
C
/*
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* Symmetric Multi Processing (SMP) support for Armada XP
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Yehuda Yitschak <yehuday@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
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* This file implements the routines for preparing the SMP infrastructure
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* and waking up the secondary CPUs
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*/
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/mbus.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include "common.h"
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#include "armada-370-xp.h"
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#include "pmsu.h"
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#include "coherency.h"
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#define AXP_BOOTROM_BASE 0xfff00000
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#define AXP_BOOTROM_SIZE 0x100000
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static struct clk *__init get_cpu_clk(int cpu)
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{
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struct clk *cpu_clk;
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struct device_node *np = of_get_cpu_node(cpu, NULL);
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if (WARN(!np, "missing cpu node\n"))
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return NULL;
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cpu_clk = of_clk_get(np, 0);
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if (WARN_ON(IS_ERR(cpu_clk)))
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return NULL;
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return cpu_clk;
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}
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static void __init set_secondary_cpus_clock(void)
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{
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int thiscpu, cpu;
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unsigned long rate;
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struct clk *cpu_clk;
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thiscpu = smp_processor_id();
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cpu_clk = get_cpu_clk(thiscpu);
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if (!cpu_clk)
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return;
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clk_prepare_enable(cpu_clk);
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rate = clk_get_rate(cpu_clk);
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/* set all the other CPU clk to the same rate than the boot CPU */
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for_each_possible_cpu(cpu) {
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if (cpu == thiscpu)
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continue;
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cpu_clk = get_cpu_clk(cpu);
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if (!cpu_clk)
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return;
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clk_set_rate(cpu_clk, rate);
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}
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}
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static void armada_xp_secondary_init(unsigned int cpu)
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{
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armada_xp_mpic_smp_cpu_init();
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}
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static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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pr_info("Booting CPU %d\n", cpu);
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armada_xp_boot_cpu(cpu, armada_xp_secondary_startup);
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return 0;
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}
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static void __init armada_xp_smp_init_cpus(void)
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{
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unsigned int ncores = num_possible_cpus();
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if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
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panic("Invalid number of CPUs in DT\n");
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}
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static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *node;
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struct resource res;
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int err;
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set_secondary_cpus_clock();
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flush_cache_all();
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set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
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/*
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* In order to boot the secondary CPUs we need to ensure
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* the bootROM is mapped at the correct address.
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*/
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node = of_find_compatible_node(NULL, NULL, "marvell,bootrom");
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if (!node)
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panic("Cannot find 'marvell,bootrom' compatible node");
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err = of_address_to_resource(node, 0, &res);
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if (err < 0)
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panic("Cannot get 'bootrom' node address");
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if (res.start != AXP_BOOTROM_BASE ||
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resource_size(&res) != AXP_BOOTROM_SIZE)
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panic("The address for the BootROM is incorrect");
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}
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struct smp_operations armada_xp_smp_ops __initdata = {
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.smp_init_cpus = armada_xp_smp_init_cpus,
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.smp_prepare_cpus = armada_xp_smp_prepare_cpus,
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.smp_secondary_init = armada_xp_secondary_init,
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.smp_boot_secondary = armada_xp_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = armada_xp_cpu_die,
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#endif
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};
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