mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-29 15:43:59 +08:00
284f5f9dba
A PCIe downstream port is a P2P bridge. Its secondary interface is
a link that should lead only to device 0 (unless ARI is enabled)[1], so
we don't probe for non-zero device numbers.
Some Stratus ftServer systems have a PCIe downstream port (02:00.0) that
leads to both an upstream port (03:00.0) and a downstream port (03:01.0),
and 03:01.0 has important devices below it:
[0000:02]-+-00.0-[03-3c]--+-00.0-[04-09]--...
\-01.0-[0a-0d]--+-[USB]
+-[NIC]
+-...
Previously, we didn't enumerate device 03:01.0, so USB and the network
didn't work. This patch adds a DMI quirk to scan all device numbers,
not just 0, below a downstream port.
Based on a patch by Prarit Bhargava.
[1] PCIe spec r3.0, sec 7.3.1
CC: Myron Stowe <mstowe@redhat.com>
CC: Don Dutile <ddutile@redhat.com>
CC: James Paradis <james.paradis@stratus.com>
CC: Matthew Wilcox <matthew.r.wilcox@intel.com>
CC: Jesse Barnes <jbarnes@virtuousgeek.org>
CC: Prarit Bhargava <prarit@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
75 lines
1.7 KiB
C
75 lines
1.7 KiB
C
/*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License
|
|
* as published by the Free Software Foundation; either version
|
|
* 2 of the License, or (at your option) any later version.
|
|
*/
|
|
#ifndef _ASM_GENERIC_PCI_BRIDGE_H
|
|
#define _ASM_GENERIC_PCI_BRIDGE_H
|
|
|
|
#ifdef __KERNEL__
|
|
|
|
enum {
|
|
/* Force re-assigning all resources (ignore firmware
|
|
* setup completely)
|
|
*/
|
|
PCI_REASSIGN_ALL_RSRC = 0x00000001,
|
|
|
|
/* Re-assign all bus numbers */
|
|
PCI_REASSIGN_ALL_BUS = 0x00000002,
|
|
|
|
/* Do not try to assign, just use existing setup */
|
|
PCI_PROBE_ONLY = 0x00000004,
|
|
|
|
/* Don't bother with ISA alignment unless the bridge has
|
|
* ISA forwarding enabled
|
|
*/
|
|
PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
|
|
|
|
/* Enable domain numbers in /proc */
|
|
PCI_ENABLE_PROC_DOMAINS = 0x00000010,
|
|
/* ... except for domain 0 */
|
|
PCI_COMPAT_DOMAIN_0 = 0x00000020,
|
|
|
|
/* PCIe downstream ports are bridges that normally lead to only a
|
|
* device 0, but if this is set, we scan all possible devices, not
|
|
* just device 0.
|
|
*/
|
|
PCI_SCAN_ALL_PCIE_DEVS = 0x00000040,
|
|
};
|
|
|
|
#ifdef CONFIG_PCI
|
|
extern unsigned int pci_flags;
|
|
|
|
static inline void pci_set_flags(int flags)
|
|
{
|
|
pci_flags = flags;
|
|
}
|
|
|
|
static inline void pci_add_flags(int flags)
|
|
{
|
|
pci_flags |= flags;
|
|
}
|
|
|
|
static inline void pci_clear_flags(int flags)
|
|
{
|
|
pci_flags &= ~flags;
|
|
}
|
|
|
|
static inline int pci_has_flag(int flag)
|
|
{
|
|
return pci_flags & flag;
|
|
}
|
|
#else
|
|
static inline void pci_set_flags(int flags) { }
|
|
static inline void pci_add_flags(int flags) { }
|
|
static inline void pci_clear_flags(int flags) { }
|
|
static inline int pci_has_flag(int flag)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_PCI */
|
|
|
|
#endif /* __KERNEL__ */
|
|
#endif /* _ASM_GENERIC_PCI_BRIDGE_H */
|