mirror of
https://github.com/edk2-porting/linux-next.git
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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
279 lines
9.8 KiB
C
279 lines
9.8 KiB
C
/*
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* include/asm-v850/v850e_uarta.h -- original V850E on-chip UART
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*
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* Copyright (C) 2001,02,03 NEC Electronics Corporation
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* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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/* This is the original V850E UART implementation is called just `UART' in
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the docs, but we name this header file <asm/v850e_uarta.h> because the
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name <asm/v850e_uart.h> is used for the common driver that handles both
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`UART' and `UARTB' implementations. */
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#ifndef __V850_V850E_UARTA_H__
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#define __V850_V850E_UARTA_H__
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/* Raw hardware interface. */
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/* The base address of the UART control registers for channel N.
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The default is the address used on the V850E/MA1. */
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#ifndef V850E_UART_BASE_ADDR
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#define V850E_UART_BASE_ADDR(n) (0xFFFFFA00 + 0x10 * (n))
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#endif
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/* Addresses of specific UART control registers for channel N.
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The defaults are the addresses used on the V850E/MA1; if a platform
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wants to redefine any of these, it must redefine them all. */
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#ifndef V850E_UART_ASIM_ADDR
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#define V850E_UART_ASIM_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x0)
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#define V850E_UART_RXB_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x2)
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#define V850E_UART_ASIS_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x3)
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#define V850E_UART_TXB_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x4)
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#define V850E_UART_ASIF_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x5)
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#define V850E_UART_CKSR_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x6)
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#define V850E_UART_BRGC_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x7)
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#endif
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/* UART config registers. */
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#define V850E_UART_ASIM(n) (*(volatile u8 *)V850E_UART_ASIM_ADDR(n))
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/* Control bits for config registers. */
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#define V850E_UART_ASIM_CAE 0x80 /* clock enable */
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#define V850E_UART_ASIM_TXE 0x40 /* transmit enable */
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#define V850E_UART_ASIM_RXE 0x20 /* receive enable */
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#define V850E_UART_ASIM_PS_MASK 0x18 /* mask covering parity-select bits */
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#define V850E_UART_ASIM_PS_NONE 0x00 /* no parity */
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#define V850E_UART_ASIM_PS_ZERO 0x08 /* zero parity */
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#define V850E_UART_ASIM_PS_ODD 0x10 /* odd parity */
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#define V850E_UART_ASIM_PS_EVEN 0x18 /* even parity */
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#define V850E_UART_ASIM_CL_8 0x04 /* char len is 8 bits (otherwise, 7) */
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#define V850E_UART_ASIM_SL_2 0x02 /* 2 stop bits (otherwise, 1) */
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#define V850E_UART_ASIM_ISRM 0x01 /* generate INTSR interrupt on errors
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(otherwise, generate INTSER) */
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/* UART serial interface status registers. */
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#define V850E_UART_ASIS(n) (*(volatile u8 *)V850E_UART_ASIS_ADDR(n))
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/* Control bits for status registers. */
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#define V850E_UART_ASIS_PE 0x04 /* parity error */
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#define V850E_UART_ASIS_FE 0x02 /* framing error */
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#define V850E_UART_ASIS_OVE 0x01 /* overrun error */
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/* UART serial interface transmission status registers. */
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#define V850E_UART_ASIF(n) (*(volatile u8 *)V850E_UART_ASIF_ADDR(n))
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#define V850E_UART_ASIF_TXBF 0x02 /* transmit buffer flag (data in TXB) */
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#define V850E_UART_ASIF_TXSF 0x01 /* transmit shift flag (sending data) */
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/* UART receive buffer register. */
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#define V850E_UART_RXB(n) (*(volatile u8 *)V850E_UART_RXB_ADDR(n))
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/* UART transmit buffer register. */
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#define V850E_UART_TXB(n) (*(volatile u8 *)V850E_UART_TXB_ADDR(n))
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/* UART baud-rate generator control registers. */
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#define V850E_UART_CKSR(n) (*(volatile u8 *)V850E_UART_CKSR_ADDR(n))
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#define V850E_UART_CKSR_MAX 11
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#define V850E_UART_BRGC(n) (*(volatile u8 *)V850E_UART_BRGC_ADDR(n))
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#define V850E_UART_BRGC_MIN 8
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#ifndef V850E_UART_CKSR_MAX_FREQ
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#define V850E_UART_CKSR_MAX_FREQ (25*1000*1000)
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#endif
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/* Calculate the minimum value for CKSR on this processor. */
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static inline unsigned v850e_uart_cksr_min (void)
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{
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int min = 0;
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unsigned freq = V850E_UART_BASE_FREQ;
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while (freq > V850E_UART_CKSR_MAX_FREQ) {
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freq >>= 1;
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min++;
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}
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return min;
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}
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/* Slightly abstract interface used by driver. */
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/* Interrupts used by the UART. */
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/* Received when the most recently transmitted character has been sent. */
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#define V850E_UART_TX_IRQ(chan) IRQ_INTST (chan)
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/* Received when a new character has been received. */
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#define V850E_UART_RX_IRQ(chan) IRQ_INTSR (chan)
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/* UART clock generator interface. */
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/* This type encapsulates a particular uart frequency. */
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typedef struct {
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unsigned clk_divlog2;
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unsigned brgen_count;
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} v850e_uart_speed_t;
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/* Calculate a uart speed from BAUD for this uart. */
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static inline v850e_uart_speed_t v850e_uart_calc_speed (unsigned baud)
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{
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v850e_uart_speed_t speed;
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/* Calculate the log2 clock divider and baud-rate counter values
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(note that the UART divides the resulting clock by 2, so
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multiply BAUD by 2 here to compensate). */
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calc_counter_params (V850E_UART_BASE_FREQ, baud * 2,
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v850e_uart_cksr_min(),
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V850E_UART_CKSR_MAX, 8/*bits*/,
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&speed.clk_divlog2, &speed.brgen_count);
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return speed;
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}
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/* Return the current speed of uart channel CHAN. */
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static inline v850e_uart_speed_t v850e_uart_speed (unsigned chan)
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{
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v850e_uart_speed_t speed;
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speed.clk_divlog2 = V850E_UART_CKSR (chan);
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speed.brgen_count = V850E_UART_BRGC (chan);
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return speed;
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}
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/* Set the current speed of uart channel CHAN. */
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static inline void v850e_uart_set_speed(unsigned chan,v850e_uart_speed_t speed)
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{
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V850E_UART_CKSR (chan) = speed.clk_divlog2;
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V850E_UART_BRGC (chan) = speed.brgen_count;
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}
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static inline int
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v850e_uart_speed_eq (v850e_uart_speed_t speed1, v850e_uart_speed_t speed2)
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{
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return speed1.clk_divlog2 == speed2.clk_divlog2
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&& speed1.brgen_count == speed2.brgen_count;
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}
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/* Minimum baud rate possible. */
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#define v850e_uart_min_baud() \
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((V850E_UART_BASE_FREQ >> V850E_UART_CKSR_MAX) / (2 * 255) + 1)
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/* Maximum baud rate possible. The error is quite high at max, though. */
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#define v850e_uart_max_baud() \
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((V850E_UART_BASE_FREQ >> v850e_uart_cksr_min()) / (2 *V850E_UART_BRGC_MIN))
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/* The `maximum' clock rate the uart can used, which is wanted (though not
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really used in any useful way) by the serial framework. */
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#define v850e_uart_max_clock() \
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((V850E_UART_BASE_FREQ >> v850e_uart_cksr_min()) / 2)
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/* UART configuration interface. */
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/* Type of the uart config register; must be a scalar. */
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typedef u16 v850e_uart_config_t;
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/* The uart hardware config register for channel CHAN. */
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#define V850E_UART_CONFIG(chan) V850E_UART_ASIM (chan)
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/* This config bit set if the uart is enabled. */
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#define V850E_UART_CONFIG_ENABLED V850E_UART_ASIM_CAE
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/* If the uart _isn't_ enabled, store this value to it to do so. */
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#define V850E_UART_CONFIG_INIT V850E_UART_ASIM_CAE
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/* Store this config value to disable the uart channel completely. */
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#define V850E_UART_CONFIG_FINI 0
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/* Setting/clearing these bits enable/disable TX/RX, respectively (but
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otherwise generally leave things running). */
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#define V850E_UART_CONFIG_RX_ENABLE V850E_UART_ASIM_RXE
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#define V850E_UART_CONFIG_TX_ENABLE V850E_UART_ASIM_TXE
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/* These masks define which config bits affect TX/RX modes, respectively. */
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#define V850E_UART_CONFIG_RX_BITS \
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(V850E_UART_ASIM_PS_MASK | V850E_UART_ASIM_CL_8 | V850E_UART_ASIM_ISRM)
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#define V850E_UART_CONFIG_TX_BITS \
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(V850E_UART_ASIM_PS_MASK | V850E_UART_ASIM_CL_8 | V850E_UART_ASIM_SL_2)
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static inline v850e_uart_config_t v850e_uart_calc_config (unsigned cflags)
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{
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v850e_uart_config_t config = 0;
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/* Figure out new configuration of control register. */
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if (cflags & CSTOPB)
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/* Number of stop bits, 1 or 2. */
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config |= V850E_UART_ASIM_SL_2;
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if ((cflags & CSIZE) == CS8)
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/* Number of data bits, 7 or 8. */
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config |= V850E_UART_ASIM_CL_8;
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if (! (cflags & PARENB))
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/* No parity check/generation. */
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config |= V850E_UART_ASIM_PS_NONE;
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else if (cflags & PARODD)
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/* Odd parity check/generation. */
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config |= V850E_UART_ASIM_PS_ODD;
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else
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/* Even parity check/generation. */
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config |= V850E_UART_ASIM_PS_EVEN;
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if (cflags & CREAD)
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/* Reading enabled. */
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config |= V850E_UART_ASIM_RXE;
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config |= V850E_UART_ASIM_CAE;
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config |= V850E_UART_ASIM_TXE; /* Writing is always enabled. */
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config |= V850E_UART_ASIM_ISRM; /* Errors generate a read-irq. */
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return config;
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}
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/* This should delay as long as necessary for a recently written config
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setting to settle, before we turn the uart back on. */
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static inline void
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v850e_uart_config_delay (v850e_uart_config_t config, v850e_uart_speed_t speed)
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{
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/* The UART may not be reset properly unless we wait at least 2
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`basic-clocks' until turning on the TXE/RXE bits again.
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A `basic clock' is the clock used by the baud-rate generator,
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i.e., the cpu clock divided by the 2^new_clk_divlog2.
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The loop takes 2 insns, so loop CYCLES / 2 times. */
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register unsigned count = 1 << speed.clk_divlog2;
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while (--count != 0)
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/* nothing */;
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}
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/* RX/TX interface. */
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/* Return true if all characters awaiting transmission on uart channel N
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have been transmitted. */
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#define v850e_uart_xmit_done(n) \
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(! (V850E_UART_ASIF(n) & V850E_UART_ASIF_TXBF))
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/* Wait for this to be true. */
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#define v850e_uart_wait_for_xmit_done(n) \
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do { } while (! v850e_uart_xmit_done (n))
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/* Return true if uart channel N is ready to transmit a character. */
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#define v850e_uart_xmit_ok(n) \
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(v850e_uart_xmit_done(n) && v850e_uart_cts(n))
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/* Wait for this to be true. */
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#define v850e_uart_wait_for_xmit_ok(n) \
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do { } while (! v850e_uart_xmit_ok (n))
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/* Write character CH to uart channel CHAN. */
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#define v850e_uart_putc(chan, ch) (V850E_UART_TXB(chan) = (ch))
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/* Return latest character read on channel CHAN. */
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#define v850e_uart_getc(chan) V850E_UART_RXB (chan)
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/* Return bit-mask of uart error status. */
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#define v850e_uart_err(chan) V850E_UART_ASIS (chan)
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/* Various error bits set in the error result. */
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#define V850E_UART_ERR_OVERRUN V850E_UART_ASIS_OVE
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#define V850E_UART_ERR_FRAME V850E_UART_ASIS_FE
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#define V850E_UART_ERR_PARITY V850E_UART_ASIS_PE
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#endif /* __V850_V850E_UARTA_H__ */
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