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2eea7f067f
Based on the RFI patching. This is required to be able to disable the speculation barrier. Only one barrier type is supported and it does nothing when the firmware does not enable it. Also re-patching modules is not supported So the only meaningful thing that can be done is patching out the speculation barrier at boot when the user says it is not wanted. Signed-off-by: Michal Suchanek <msuchanek@suse.de> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
97 lines
3.3 KiB
C
97 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
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*/
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#ifndef _ASM_POWERPC_BARRIER_H
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#define _ASM_POWERPC_BARRIER_H
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/*
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* Memory barrier.
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* The sync instruction guarantees that all memory accesses initiated
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* by this processor have been performed (with respect to all other
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* mechanisms that access memory). The eieio instruction is a barrier
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* providing an ordering (separately) for (a) cacheable stores and (b)
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* loads and stores to non-cacheable memory (e.g. I/O devices).
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*
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* mb() prevents loads and stores being reordered across this point.
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* rmb() prevents loads being reordered across this point.
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* wmb() prevents stores being reordered across this point.
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* read_barrier_depends() prevents data-dependent loads being reordered
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* across this point (nop on PPC).
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*
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* *mb() variants without smp_ prefix must order all types of memory
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* operations with one another. sync is the only instruction sufficient
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* to do this.
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*
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* For the smp_ barriers, ordering is for cacheable memory operations
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* only. We have to use the sync instruction for smp_mb(), since lwsync
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* doesn't order loads with respect to previous stores. Lwsync can be
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* used for smp_rmb() and smp_wmb().
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*
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* However, on CPUs that don't support lwsync, lwsync actually maps to a
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* heavy-weight sync, so smp_wmb() can be a lighter-weight eieio.
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*/
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#define mb() __asm__ __volatile__ ("sync" : : : "memory")
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#define rmb() __asm__ __volatile__ ("sync" : : : "memory")
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#define wmb() __asm__ __volatile__ ("sync" : : : "memory")
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/* The sub-arch has lwsync */
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#if defined(__powerpc64__) || defined(CONFIG_PPC_E500MC)
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# define SMPWMB LWSYNC
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#else
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# define SMPWMB eieio
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#endif
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#define __lwsync() __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory")
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#define dma_rmb() __lwsync()
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#define dma_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory")
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#define __smp_lwsync() __lwsync()
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#define __smp_mb() mb()
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#define __smp_rmb() __lwsync()
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#define __smp_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory")
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/*
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* This is a barrier which prevents following instructions from being
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* started until the value of the argument x is known. For example, if
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* x is a variable loaded from memory, this prevents following
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* instructions from being executed until the load has been performed.
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*/
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#define data_barrier(x) \
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asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
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#define __smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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__smp_lwsync(); \
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WRITE_ONCE(*p, v); \
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} while (0)
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#define __smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = READ_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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__smp_lwsync(); \
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___p1; \
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})
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#ifdef CONFIG_PPC_BOOK3S_64
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/*
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* Prevent execution of subsequent instructions until preceding branches have
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* been fully resolved and are no longer executing speculatively.
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*/
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#define barrier_nospec_asm NOSPEC_BARRIER_FIXUP_SECTION; nop
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// This also acts as a compiler barrier due to the memory clobber.
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#define barrier_nospec() asm (stringify_in_c(barrier_nospec_asm) ::: "memory")
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#else /* !CONFIG_PPC_BOOK3S_64 */
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#define barrier_nospec_asm
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#define barrier_nospec()
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#endif
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#include <asm-generic/barrier.h>
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#endif /* _ASM_POWERPC_BARRIER_H */
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