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mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-26 06:04:14 +08:00
linux-next/arch/arc/include
Linus Torvalds ee89252b9e ARC changes for 4.14-rc1
- support for HSDK board hosting a Quad core HS38x4 based SoC running @ 1 GHz
    (and some prerrquisite changes such as ability to scoot the kernel code/data
     from start of memory map etc)
 
  - Quite a few updates for EZChip (Mellanox) platform
 
  - Fixes to fault/exception printing
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJZstaxAAoJEGnX8d3iisJe5I0QAIExIdU5/V/bgJ7EJJaa6qW4
 VxB5HXzbwOuIx/3i/uv4AwBIoeZIzuRQnjwf2dzTJms5vjT2zR08DGYIBmtSAA23
 ZUmpZVd865IItLCRM7WOerP6B6gaHaObzNlZoo2d8rVnz0fruc5Td4PDC1Esfs7D
 vA4aITbiG6FsJMYFeYR6IKJbM8D1CmB2Gm1gEPIifniJ9dy/V9Xi5ttvISpVJSNx
 QMb6PDHVEpkOBypUEJKeoClFZlkeqscejjXmZ3QrhoeHM//3hX8MdvyvFBmoCY4t
 YpmmrfmoCupwFFn7+XDwYqDyYvJk/H84n64tUcpM7PLqCuw4BaMhd3KTjkTwvsnN
 H5NAhqbHIW3r4a9esn53yvgY8zk9i6U7qmhKpEwkUQTtUZ7XrdfL1H1t08cqtxPX
 /eFBkeKNshJy8EU02MewtxvWXON3RoJC3qgHoLkrj+iq5HTQjaDEahbQNm+rnXFI
 EdRMBwPX2sXOvB/m/jQYjz6QM1QTl6zHy+tXbBpATIqgRxsp6SIInqGmq7fC032a
 K7zPWo2Vf2LLl4ifhFJaYwbrQotqDGe/F72K1C5RcWKLnhMPdLgZ4Lwf0NcJTeDt
 DjmqUFXwNdQ2Ydw0B9JxeTddVCzdLHPQqxOOvvBI0vvgsF8AFmAmx2QhMdQTsZJr
 73mD3udrQN48yYzAIZQf
 =w8CJ
 -----END PGP SIGNATURE-----

Merge tag 'arc-4.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc

Pull ARC updates from Vineet Gupta:

 - Support for HSDK board hosting a Quad core HS38x4 based SoC running
   @1GHz (and some prerrquisite changes such as ability to scoot the
   kernel code/data from start of memory map etc)

 - Quite a few updates for EZChip (Mellanox) platform

 - Fixes to fault/exception printing

* tag 'arc-4.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (26 commits)
  ARC: Re-enable MMU upon Machine Check exception
  ARC: Show fault information passed to show_kernel_fault_diag()
  ARC: [plat-hsdk] initial port for HSDK board
  ARC: mm: Decouple RAM base address from kernel link address
  ARCv2: IOC: Tighten up the contraints (specifically base / size alignment)
  ARC: [plat-axs103] refactor the DT fudging code
  ARC: [plat-axs103] use clk driver #2: Add core pll node to DT to manage cpu clk
  ARC: [plat-axs103] use clk driver #1: Get rid of platform specific cpu clk setting
  ARCv2: SLC: provide a line based flush routine for debugging
  ARC: Hardcode ARCH_DMA_MINALIGN to max line length we may have
  ARC: [plat-eznps] handle extra aux regs #2: kernel/entry exit
  ARC: [plat-eznps] handle extra aux regs #1: save/restore on context switch
  ARC: [plat-eznps] avoid toggling of DPC register
  ARC: [plat-eznps] Update the init sequence of aux regs per cpu.
  ARC: [plat-eznps] new command line argument for HW scheduler at MTM
  ARC: set boot print log level to PR_INFO
  ARC: [plat-eznps] Handle user memory error same in simulation and silicon
  ARC: [plat-eznps] use schd.wft instruction instead of sleep at idle task
  ARC: create cpu specific version of arch_cpu_idle()
  ARC: [plat-eznps] spinlock aware for MTM
  ...
2017-09-08 16:02:18 -07:00
..
asm ARC changes for 4.14-rc1 2017-09-08 16:02:18 -07:00
uapi/asm arc: move generic-y of exported headers to uapi/asm/Kbuild 2017-07-10 03:43:21 +09:00