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86f887c105
Without this, the interrupts for I2C, VIN, GPIO, SDHC, HSCIF and HPB-DMAC are sent to the SH processor. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
66 lines
2.0 KiB
C
66 lines
2.0 KiB
C
/*
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* r8a7779 processor support - INTC hardware block
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*
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* Copyright (C) 2011 Renesas Solutions Corp.
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* Copyright (C) 2011 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <mach/common.h>
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#include <mach/intc.h>
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#include <mach/r8a7779.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#define INT2SMSKCR0 0xfe7822a0
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#define INT2SMSKCR1 0xfe7822a4
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#define INT2SMSKCR2 0xfe7822a8
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#define INT2SMSKCR3 0xfe7822ac
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#define INT2SMSKCR4 0xfe7822b0
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#define INT2NTSR0 0xfe700060
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#define INT2NTSR1 0xfe700064
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static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
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{
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return 0; /* always allow wakeup */
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}
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void __init r8a7779_init_irq(void)
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{
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void __iomem *gic_dist_base = IOMEM(0xf0001000);
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void __iomem *gic_cpu_base = IOMEM(0xf0000100);
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/* use GIC to handle interrupts */
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gic_init(0, 29, gic_dist_base, gic_cpu_base);
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gic_arch_extn.irq_set_wake = r8a7779_set_wake;
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/* route all interrupts to ARM */
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__raw_writel(0xffffffff, INT2NTSR0);
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__raw_writel(0x3fffffff, INT2NTSR1);
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/* unmask all known interrupts in INTCS2 */
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__raw_writel(0xfffffff0, INT2SMSKCR0);
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__raw_writel(0xfff7ffff, INT2SMSKCR1);
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__raw_writel(0xfffbffdf, INT2SMSKCR2);
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__raw_writel(0xbffffffc, INT2SMSKCR3);
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__raw_writel(0x003fee3f, INT2SMSKCR4);
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}
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