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19a8d6b760
04c81c7293("MIPS: PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooks") moved the PCI IRQ fixup to the new host bridge map/swizzle_irq() hooks mechanism. Those hooks can also be called after boot, when all the __init/__initdata/__initconst sections have been freed. Therefore, functions called by them (and the data they refer to) must not be marked as __init/__initdata/__initconst lest compilation trigger section mismatch warnings. Fix all the board files map_irq() hooks by simply removing the respective __init/__initdata/__initconst section markers and by adding another persistent hook IRQ map for the txx9 board files. Fixes:04c81c7293("MIPS: PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooks") Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Steve French <smfrench@gmail.com>
143 lines
4.0 KiB
C
143 lines
4.0 KiB
C
/*
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* Based on linux/arch/mips/txx9/rbtx4938/setup.c,
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* and RBTX49xx patch from CELF patch archive.
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*
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* Copyright 2001, 2003-2005 MontaVista Software Inc.
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* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
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* (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <asm/txx9/generic.h>
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#include <asm/txx9/tx4938.h>
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int __init tx4938_report_pciclk(void)
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{
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int pciclk = 0;
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pr_info("PCIC --%s PCICLK:",
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(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) ?
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" PCI66" : "");
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if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_PCICLKEN_ALL) {
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u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg);
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switch ((unsigned long)ccfg &
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TX4938_CCFG_PCIDIVMODE_MASK) {
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case TX4938_CCFG_PCIDIVMODE_4:
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pciclk = txx9_cpu_clock / 4; break;
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case TX4938_CCFG_PCIDIVMODE_4_5:
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pciclk = txx9_cpu_clock * 2 / 9; break;
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case TX4938_CCFG_PCIDIVMODE_5:
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pciclk = txx9_cpu_clock / 5; break;
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case TX4938_CCFG_PCIDIVMODE_5_5:
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pciclk = txx9_cpu_clock * 2 / 11; break;
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case TX4938_CCFG_PCIDIVMODE_8:
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pciclk = txx9_cpu_clock / 8; break;
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case TX4938_CCFG_PCIDIVMODE_9:
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pciclk = txx9_cpu_clock / 9; break;
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case TX4938_CCFG_PCIDIVMODE_10:
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pciclk = txx9_cpu_clock / 10; break;
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case TX4938_CCFG_PCIDIVMODE_11:
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pciclk = txx9_cpu_clock / 11; break;
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}
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pr_cont("Internal(%u.%uMHz)",
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(pciclk + 50000) / 1000000,
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((pciclk + 50000) / 100000) % 10);
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} else {
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pr_cont("External");
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pciclk = -1;
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}
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pr_cont("\n");
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return pciclk;
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}
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void __init tx4938_report_pci1clk(void)
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{
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__u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg);
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unsigned int pciclk =
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txx9_gbus_clock / ((ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2);
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pr_info("PCIC1 -- %sPCICLK:%u.%uMHz\n",
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(ccfg & TX4938_CCFG_PCI1_66) ? "PCI66 " : "",
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(pciclk + 50000) / 1000000,
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((pciclk + 50000) / 100000) % 10);
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}
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int __init tx4938_pciclk66_setup(void)
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{
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int pciclk;
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/* Assert M66EN */
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tx4938_ccfg_set(TX4938_CCFG_PCI66);
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/* Double PCICLK (if possible) */
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if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_PCICLKEN_ALL) {
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unsigned int pcidivmode = 0;
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u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg);
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pcidivmode = (unsigned long)ccfg &
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TX4938_CCFG_PCIDIVMODE_MASK;
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switch (pcidivmode) {
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case TX4938_CCFG_PCIDIVMODE_8:
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case TX4938_CCFG_PCIDIVMODE_4:
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pcidivmode = TX4938_CCFG_PCIDIVMODE_4;
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pciclk = txx9_cpu_clock / 4;
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break;
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case TX4938_CCFG_PCIDIVMODE_9:
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case TX4938_CCFG_PCIDIVMODE_4_5:
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pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5;
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pciclk = txx9_cpu_clock * 2 / 9;
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break;
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case TX4938_CCFG_PCIDIVMODE_10:
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case TX4938_CCFG_PCIDIVMODE_5:
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pcidivmode = TX4938_CCFG_PCIDIVMODE_5;
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pciclk = txx9_cpu_clock / 5;
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break;
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case TX4938_CCFG_PCIDIVMODE_11:
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case TX4938_CCFG_PCIDIVMODE_5_5:
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default:
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pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5;
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pciclk = txx9_cpu_clock * 2 / 11;
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break;
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}
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tx4938_ccfg_change(TX4938_CCFG_PCIDIVMODE_MASK,
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pcidivmode);
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pr_debug("PCICLK: ccfg:%08lx\n",
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(unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg));
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} else
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pciclk = -1;
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return pciclk;
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}
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int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot)
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{
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if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4938_pcic1ptr) {
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switch (slot) {
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case TX4927_PCIC_IDSEL_AD_TO_SLOT(31):
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if (__raw_readq(&tx4938_ccfgptr->pcfg) &
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TX4938_PCFG_ETH0_SEL)
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return TXX9_IRQ_BASE + TX4938_IR_ETH0;
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break;
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case TX4927_PCIC_IDSEL_AD_TO_SLOT(30):
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if (__raw_readq(&tx4938_ccfgptr->pcfg) &
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TX4938_PCFG_ETH1_SEL)
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return TXX9_IRQ_BASE + TX4938_IR_ETH1;
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break;
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}
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return 0;
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}
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return -1;
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}
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void __init tx4938_setup_pcierr_irq(void)
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{
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if (request_irq(TXX9_IRQ_BASE + TX4938_IR_PCIERR,
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tx4927_pcierr_interrupt,
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0, "PCI error",
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(void *)TX4927_PCIC_REG))
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pr_warn("Failed to request irq for PCIERR\n");
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}
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