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52b31bcc93
The equivalent of both of these are now done via macro magic when the relevant register calls are made. The actual structure elements will shortly go away. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Lars-Peter Clausen <lars@metafoo.de>
596 lines
14 KiB
C
596 lines
14 KiB
C
/*
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* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/bitops.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/iio/iio.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mutex.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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/* IADC register and bit definition */
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#define IADC_REVISION2 0x1
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#define IADC_REVISION2_SUPPORTED_IADC 1
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#define IADC_PERPH_TYPE 0x4
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#define IADC_PERPH_TYPE_ADC 8
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#define IADC_PERPH_SUBTYPE 0x5
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#define IADC_PERPH_SUBTYPE_IADC 3
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#define IADC_STATUS1 0x8
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#define IADC_STATUS1_OP_MODE 4
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#define IADC_STATUS1_REQ_STS BIT(1)
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#define IADC_STATUS1_EOC BIT(0)
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#define IADC_STATUS1_REQ_STS_EOC_MASK 0x3
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#define IADC_MODE_CTL 0x40
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#define IADC_OP_MODE_SHIFT 3
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#define IADC_OP_MODE_NORMAL 0
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#define IADC_TRIM_EN BIT(0)
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#define IADC_EN_CTL1 0x46
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#define IADC_EN_CTL1_SET BIT(7)
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#define IADC_CH_SEL_CTL 0x48
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#define IADC_DIG_PARAM 0x50
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#define IADC_DIG_DEC_RATIO_SEL_SHIFT 2
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#define IADC_HW_SETTLE_DELAY 0x51
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#define IADC_CONV_REQ 0x52
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#define IADC_CONV_REQ_SET BIT(7)
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#define IADC_FAST_AVG_CTL 0x5a
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#define IADC_FAST_AVG_EN 0x5b
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#define IADC_FAST_AVG_EN_SET BIT(7)
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#define IADC_PERH_RESET_CTL3 0xda
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#define IADC_FOLLOW_WARM_RB BIT(2)
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#define IADC_DATA 0x60 /* 16 bits */
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#define IADC_SEC_ACCESS 0xd0
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#define IADC_SEC_ACCESS_DATA 0xa5
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#define IADC_NOMINAL_RSENSE 0xf4
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#define IADC_NOMINAL_RSENSE_SIGN_MASK BIT(7)
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#define IADC_REF_GAIN_MICRO_VOLTS 17857
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#define IADC_INT_RSENSE_DEVIATION 15625 /* nano Ohms per bit */
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#define IADC_INT_RSENSE_IDEAL_VALUE 10000 /* micro Ohms */
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#define IADC_INT_RSENSE_DEFAULT_VALUE 7800 /* micro Ohms */
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#define IADC_INT_RSENSE_DEFAULT_GF 9000 /* micro Ohms */
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#define IADC_INT_RSENSE_DEFAULT_SMIC 9700 /* micro Ohms */
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#define IADC_CONV_TIME_MIN_US 2000
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#define IADC_CONV_TIME_MAX_US 2100
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#define IADC_DEF_PRESCALING 0 /* 1:1 */
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#define IADC_DEF_DECIMATION 0 /* 512 */
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#define IADC_DEF_HW_SETTLE_TIME 0 /* 0 us */
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#define IADC_DEF_AVG_SAMPLES 0 /* 1 sample */
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/* IADC channel list */
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#define IADC_INT_RSENSE 0
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#define IADC_EXT_RSENSE 1
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#define IADC_GAIN_17P857MV 3
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#define IADC_EXT_OFFSET_CSP_CSN 5
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#define IADC_INT_OFFSET_CSP2_CSN2 6
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/**
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* struct iadc_chip - IADC Current ADC device structure.
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* @regmap: regmap for register read/write.
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* @dev: This device pointer.
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* @base: base offset for the ADC peripheral.
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* @rsense: Values of the internal and external sense resister in micro Ohms.
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* @poll_eoc: Poll for end of conversion instead of waiting for IRQ.
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* @offset: Raw offset values for the internal and external channels.
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* @gain: Raw gain of the channels.
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* @lock: ADC lock for access to the peripheral.
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* @complete: ADC notification after end of conversion interrupt is received.
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*/
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struct iadc_chip {
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struct regmap *regmap;
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struct device *dev;
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u16 base;
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bool poll_eoc;
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u32 rsense[2];
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u16 offset[2];
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u16 gain;
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struct mutex lock;
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struct completion complete;
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};
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static int iadc_read(struct iadc_chip *iadc, u16 offset, u8 *data)
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{
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unsigned int val;
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int ret;
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ret = regmap_read(iadc->regmap, iadc->base + offset, &val);
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if (ret < 0)
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return ret;
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*data = val;
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return 0;
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}
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static int iadc_write(struct iadc_chip *iadc, u16 offset, u8 data)
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{
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return regmap_write(iadc->regmap, iadc->base + offset, data);
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}
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static int iadc_reset(struct iadc_chip *iadc)
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{
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u8 data;
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int ret;
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ret = iadc_write(iadc, IADC_SEC_ACCESS, IADC_SEC_ACCESS_DATA);
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if (ret < 0)
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return ret;
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ret = iadc_read(iadc, IADC_PERH_RESET_CTL3, &data);
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if (ret < 0)
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return ret;
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ret = iadc_write(iadc, IADC_SEC_ACCESS, IADC_SEC_ACCESS_DATA);
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if (ret < 0)
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return ret;
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data |= IADC_FOLLOW_WARM_RB;
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return iadc_write(iadc, IADC_PERH_RESET_CTL3, data);
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}
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static int iadc_set_state(struct iadc_chip *iadc, bool state)
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{
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return iadc_write(iadc, IADC_EN_CTL1, state ? IADC_EN_CTL1_SET : 0);
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}
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static void iadc_status_show(struct iadc_chip *iadc)
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{
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u8 mode, sta1, chan, dig, en, req;
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int ret;
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ret = iadc_read(iadc, IADC_MODE_CTL, &mode);
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if (ret < 0)
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return;
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ret = iadc_read(iadc, IADC_DIG_PARAM, &dig);
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if (ret < 0)
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return;
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ret = iadc_read(iadc, IADC_CH_SEL_CTL, &chan);
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if (ret < 0)
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return;
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ret = iadc_read(iadc, IADC_CONV_REQ, &req);
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if (ret < 0)
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return;
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ret = iadc_read(iadc, IADC_STATUS1, &sta1);
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if (ret < 0)
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return;
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ret = iadc_read(iadc, IADC_EN_CTL1, &en);
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if (ret < 0)
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return;
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dev_err(iadc->dev,
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"mode:%02x en:%02x chan:%02x dig:%02x req:%02x sta1:%02x\n",
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mode, en, chan, dig, req, sta1);
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}
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static int iadc_configure(struct iadc_chip *iadc, int channel)
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{
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u8 decim, mode;
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int ret;
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/* Mode selection */
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mode = (IADC_OP_MODE_NORMAL << IADC_OP_MODE_SHIFT) | IADC_TRIM_EN;
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ret = iadc_write(iadc, IADC_MODE_CTL, mode);
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if (ret < 0)
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return ret;
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/* Channel selection */
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ret = iadc_write(iadc, IADC_CH_SEL_CTL, channel);
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if (ret < 0)
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return ret;
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/* Digital parameter setup */
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decim = IADC_DEF_DECIMATION << IADC_DIG_DEC_RATIO_SEL_SHIFT;
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ret = iadc_write(iadc, IADC_DIG_PARAM, decim);
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if (ret < 0)
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return ret;
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/* HW settle time delay */
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ret = iadc_write(iadc, IADC_HW_SETTLE_DELAY, IADC_DEF_HW_SETTLE_TIME);
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if (ret < 0)
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return ret;
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ret = iadc_write(iadc, IADC_FAST_AVG_CTL, IADC_DEF_AVG_SAMPLES);
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if (ret < 0)
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return ret;
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if (IADC_DEF_AVG_SAMPLES)
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ret = iadc_write(iadc, IADC_FAST_AVG_EN, IADC_FAST_AVG_EN_SET);
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else
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ret = iadc_write(iadc, IADC_FAST_AVG_EN, 0);
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if (ret < 0)
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return ret;
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if (!iadc->poll_eoc)
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reinit_completion(&iadc->complete);
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ret = iadc_set_state(iadc, true);
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if (ret < 0)
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return ret;
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/* Request conversion */
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return iadc_write(iadc, IADC_CONV_REQ, IADC_CONV_REQ_SET);
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}
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static int iadc_poll_wait_eoc(struct iadc_chip *iadc, unsigned int interval_us)
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{
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unsigned int count, retry;
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int ret;
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u8 sta1;
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retry = interval_us / IADC_CONV_TIME_MIN_US;
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for (count = 0; count < retry; count++) {
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ret = iadc_read(iadc, IADC_STATUS1, &sta1);
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if (ret < 0)
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return ret;
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sta1 &= IADC_STATUS1_REQ_STS_EOC_MASK;
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if (sta1 == IADC_STATUS1_EOC)
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return 0;
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usleep_range(IADC_CONV_TIME_MIN_US, IADC_CONV_TIME_MAX_US);
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}
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iadc_status_show(iadc);
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return -ETIMEDOUT;
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}
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static int iadc_read_result(struct iadc_chip *iadc, u16 *data)
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{
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return regmap_bulk_read(iadc->regmap, iadc->base + IADC_DATA, data, 2);
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}
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static int iadc_do_conversion(struct iadc_chip *iadc, int chan, u16 *data)
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{
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unsigned int wait;
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int ret;
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ret = iadc_configure(iadc, chan);
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if (ret < 0)
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goto exit;
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wait = BIT(IADC_DEF_AVG_SAMPLES) * IADC_CONV_TIME_MIN_US * 2;
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if (iadc->poll_eoc) {
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ret = iadc_poll_wait_eoc(iadc, wait);
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} else {
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ret = wait_for_completion_timeout(&iadc->complete,
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usecs_to_jiffies(wait));
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if (!ret)
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ret = -ETIMEDOUT;
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else
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/* double check conversion status */
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ret = iadc_poll_wait_eoc(iadc, IADC_CONV_TIME_MIN_US);
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}
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if (!ret)
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ret = iadc_read_result(iadc, data);
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exit:
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iadc_set_state(iadc, false);
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if (ret < 0)
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dev_err(iadc->dev, "conversion failed\n");
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return ret;
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}
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static int iadc_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct iadc_chip *iadc = iio_priv(indio_dev);
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s32 isense_ua, vsense_uv;
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u16 adc_raw, vsense_raw;
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int ret;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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mutex_lock(&iadc->lock);
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ret = iadc_do_conversion(iadc, chan->channel, &adc_raw);
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mutex_unlock(&iadc->lock);
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if (ret < 0)
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return ret;
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vsense_raw = adc_raw - iadc->offset[chan->channel];
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vsense_uv = vsense_raw * IADC_REF_GAIN_MICRO_VOLTS;
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vsense_uv /= (s32)iadc->gain - iadc->offset[chan->channel];
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isense_ua = vsense_uv / iadc->rsense[chan->channel];
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dev_dbg(iadc->dev, "off %d gain %d adc %d %duV I %duA\n",
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iadc->offset[chan->channel], iadc->gain,
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adc_raw, vsense_uv, isense_ua);
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*val = isense_ua;
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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*val = 0;
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*val2 = 1000;
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return IIO_VAL_INT_PLUS_MICRO;
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}
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return -EINVAL;
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}
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static const struct iio_info iadc_info = {
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.read_raw = iadc_read_raw,
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};
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static irqreturn_t iadc_isr(int irq, void *dev_id)
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{
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struct iadc_chip *iadc = dev_id;
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complete(&iadc->complete);
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return IRQ_HANDLED;
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}
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static int iadc_update_offset(struct iadc_chip *iadc)
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{
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int ret;
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ret = iadc_do_conversion(iadc, IADC_GAIN_17P857MV, &iadc->gain);
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if (ret < 0)
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return ret;
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ret = iadc_do_conversion(iadc, IADC_INT_OFFSET_CSP2_CSN2,
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&iadc->offset[IADC_INT_RSENSE]);
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if (ret < 0)
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return ret;
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if (iadc->gain == iadc->offset[IADC_INT_RSENSE]) {
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dev_err(iadc->dev, "error: internal offset == gain %d\n",
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iadc->gain);
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return -EINVAL;
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}
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ret = iadc_do_conversion(iadc, IADC_EXT_OFFSET_CSP_CSN,
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&iadc->offset[IADC_EXT_RSENSE]);
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if (ret < 0)
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return ret;
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if (iadc->gain == iadc->offset[IADC_EXT_RSENSE]) {
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dev_err(iadc->dev, "error: external offset == gain %d\n",
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iadc->gain);
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return -EINVAL;
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}
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return 0;
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}
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static int iadc_version_check(struct iadc_chip *iadc)
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{
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u8 val;
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int ret;
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ret = iadc_read(iadc, IADC_PERPH_TYPE, &val);
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if (ret < 0)
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return ret;
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if (val < IADC_PERPH_TYPE_ADC) {
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dev_err(iadc->dev, "%d is not ADC\n", val);
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return -EINVAL;
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}
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ret = iadc_read(iadc, IADC_PERPH_SUBTYPE, &val);
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if (ret < 0)
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return ret;
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if (val < IADC_PERPH_SUBTYPE_IADC) {
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dev_err(iadc->dev, "%d is not IADC\n", val);
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return -EINVAL;
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}
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ret = iadc_read(iadc, IADC_REVISION2, &val);
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if (ret < 0)
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return ret;
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if (val < IADC_REVISION2_SUPPORTED_IADC) {
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dev_err(iadc->dev, "revision %d not supported\n", val);
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return -EINVAL;
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}
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return 0;
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}
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static int iadc_rsense_read(struct iadc_chip *iadc, struct device_node *node)
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{
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int ret, sign, int_sense;
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u8 deviation;
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ret = of_property_read_u32(node, "qcom,external-resistor-micro-ohms",
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&iadc->rsense[IADC_EXT_RSENSE]);
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if (ret < 0)
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iadc->rsense[IADC_EXT_RSENSE] = IADC_INT_RSENSE_IDEAL_VALUE;
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if (!iadc->rsense[IADC_EXT_RSENSE]) {
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dev_err(iadc->dev, "external resistor can't be zero Ohms");
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return -EINVAL;
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}
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ret = iadc_read(iadc, IADC_NOMINAL_RSENSE, &deviation);
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if (ret < 0)
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return ret;
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/*
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* Deviation value stored is an offset from 10 mili Ohms, bit 7 is
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* the sign, the remaining bits have an LSB of 15625 nano Ohms.
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*/
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sign = (deviation & IADC_NOMINAL_RSENSE_SIGN_MASK) ? -1 : 1;
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deviation &= ~IADC_NOMINAL_RSENSE_SIGN_MASK;
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/* Scale it to nono Ohms */
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int_sense = IADC_INT_RSENSE_IDEAL_VALUE * 1000;
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int_sense += sign * deviation * IADC_INT_RSENSE_DEVIATION;
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int_sense /= 1000; /* micro Ohms */
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iadc->rsense[IADC_INT_RSENSE] = int_sense;
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return 0;
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}
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static const struct iio_chan_spec iadc_channels[] = {
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{
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.type = IIO_CURRENT,
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.datasheet_name = "INTERNAL_RSENSE",
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.channel = 0,
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
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BIT(IIO_CHAN_INFO_SCALE),
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.indexed = 1,
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},
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{
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.type = IIO_CURRENT,
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.datasheet_name = "EXTERNAL_RSENSE",
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.channel = 1,
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
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BIT(IIO_CHAN_INFO_SCALE),
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.indexed = 1,
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},
|
|
};
|
|
|
|
static int iadc_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *node = pdev->dev.of_node;
|
|
struct device *dev = &pdev->dev;
|
|
struct iio_dev *indio_dev;
|
|
struct iadc_chip *iadc;
|
|
int ret, irq_eoc;
|
|
u32 res;
|
|
|
|
indio_dev = devm_iio_device_alloc(dev, sizeof(*iadc));
|
|
if (!indio_dev)
|
|
return -ENOMEM;
|
|
|
|
iadc = iio_priv(indio_dev);
|
|
iadc->dev = dev;
|
|
|
|
iadc->regmap = dev_get_regmap(dev->parent, NULL);
|
|
if (!iadc->regmap)
|
|
return -ENODEV;
|
|
|
|
init_completion(&iadc->complete);
|
|
mutex_init(&iadc->lock);
|
|
|
|
ret = of_property_read_u32(node, "reg", &res);
|
|
if (ret < 0)
|
|
return -ENODEV;
|
|
|
|
iadc->base = res;
|
|
|
|
ret = iadc_version_check(iadc);
|
|
if (ret < 0)
|
|
return -ENODEV;
|
|
|
|
ret = iadc_rsense_read(iadc, node);
|
|
if (ret < 0)
|
|
return -ENODEV;
|
|
|
|
dev_dbg(iadc->dev, "sense resistors %d and %d micro Ohm\n",
|
|
iadc->rsense[IADC_INT_RSENSE],
|
|
iadc->rsense[IADC_EXT_RSENSE]);
|
|
|
|
irq_eoc = platform_get_irq(pdev, 0);
|
|
if (irq_eoc == -EPROBE_DEFER)
|
|
return irq_eoc;
|
|
|
|
if (irq_eoc < 0)
|
|
iadc->poll_eoc = true;
|
|
|
|
ret = iadc_reset(iadc);
|
|
if (ret < 0) {
|
|
dev_err(dev, "reset failed\n");
|
|
return ret;
|
|
}
|
|
|
|
if (!iadc->poll_eoc) {
|
|
ret = devm_request_irq(dev, irq_eoc, iadc_isr, 0,
|
|
"spmi-iadc", iadc);
|
|
if (!ret)
|
|
enable_irq_wake(irq_eoc);
|
|
else
|
|
return ret;
|
|
} else {
|
|
device_init_wakeup(iadc->dev, 1);
|
|
}
|
|
|
|
ret = iadc_update_offset(iadc);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed offset calibration\n");
|
|
return ret;
|
|
}
|
|
|
|
indio_dev->dev.parent = dev;
|
|
indio_dev->dev.of_node = node;
|
|
indio_dev->name = pdev->name;
|
|
indio_dev->modes = INDIO_DIRECT_MODE;
|
|
indio_dev->info = &iadc_info;
|
|
indio_dev->channels = iadc_channels;
|
|
indio_dev->num_channels = ARRAY_SIZE(iadc_channels);
|
|
|
|
return devm_iio_device_register(dev, indio_dev);
|
|
}
|
|
|
|
static const struct of_device_id iadc_match_table[] = {
|
|
{ .compatible = "qcom,spmi-iadc" },
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, iadc_match_table);
|
|
|
|
static struct platform_driver iadc_driver = {
|
|
.driver = {
|
|
.name = "qcom-spmi-iadc",
|
|
.of_match_table = iadc_match_table,
|
|
},
|
|
.probe = iadc_probe,
|
|
};
|
|
|
|
module_platform_driver(iadc_driver);
|
|
|
|
MODULE_ALIAS("platform:qcom-spmi-iadc");
|
|
MODULE_DESCRIPTION("Qualcomm SPMI PMIC current ADC driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
|