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The Macronix mx66u2g45g is a 1.8V, 2Gbit (256MB) device that supports x1, x2, or x4 operation. Tested on Pensando SoC hardware with a cadence quadspi controller via drivers/spi/spi-cadence-quadspi.c, in x2 mode at 50MHz. - random data write, erase, read - verified erase operations - random data write, read/compare - verified write/read operations Signed-off-by: David Clear <dac2@pensando.io> Acked-by: Shannon Nelson <snelson@pensando.io> Link: https://lore.kernel.org/r/20200720163656.38006-2-dac2@pensando.io Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
111 lines
4.1 KiB
C
111 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2005, Intec Automation Inc.
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* Copyright (C) 2014, Freescale Semiconductor, Inc.
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*/
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#include <linux/mtd/spi-nor.h>
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#include "core.h"
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static int
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mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt,
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struct spi_nor_flash_parameter *params)
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{
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/*
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* MX25L25635F supports 4B opcodes but MX25L25635E does not.
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* Unfortunately, Macronix has re-used the same JEDEC ID for both
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* variants which prevents us from defining a new entry in the parts
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* table.
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* We need a way to differentiate MX25L25635E and MX25L25635F, and it
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* seems that the F version advertises support for Fast Read 4-4-4 in
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* its BFPT table.
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*/
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if (bfpt->dwords[BFPT_DWORD(5)] & BFPT_DWORD5_FAST_READ_4_4_4)
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nor->flags |= SNOR_F_4B_OPCODES;
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return 0;
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}
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static struct spi_nor_fixups mx25l25635_fixups = {
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.post_bfpt = mx25l25635_post_bfpt_fixups,
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};
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static const struct flash_info macronix_parts[] = {
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/* Macronix */
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{ "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
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{ "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
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{ "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
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{ "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
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{ "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
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{ "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
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{ "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
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{ "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
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{ "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
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{ "mx25u3235f", INFO(0xc22536, 0, 64 * 1024, 64,
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SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) },
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{ "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) },
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{ "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
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{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
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{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
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{ "mx25r1635f", INFO(0xc22815, 0, 64 * 1024, 32,
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SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "mx25r3235f", INFO(0xc22816, 0, 64 * 1024, 64,
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SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256,
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SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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.fixups = &mx25l25635_fixups },
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{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512,
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SECT_4K | SPI_NOR_4B_OPCODES) },
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{ "mx25u51245g", INFO(0xc2253a, 0, 64 * 1024, 1024,
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SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
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{ "mx25v8035f", INFO(0xc22314, 0, 64 * 1024, 16,
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SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
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{ "mx25l51245g", INFO(0xc2201a, 0, 64 * 1024, 1024,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES) },
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{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES) },
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{ "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024,
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SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
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{ "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048,
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SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048,
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SPI_NOR_QUAD_READ) },
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{ "mx66u2g45g", INFO(0xc2253c, 0, 64 * 1024, 4096,
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SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
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};
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static void macronix_default_init(struct spi_nor *nor)
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{
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nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
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nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode;
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}
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static const struct spi_nor_fixups macronix_fixups = {
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.default_init = macronix_default_init,
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};
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const struct spi_nor_manufacturer spi_nor_macronix = {
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.name = "macronix",
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.parts = macronix_parts,
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.nparts = ARRAY_SIZE(macronix_parts),
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.fixups = ¯onix_fixups,
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};
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