mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-22 12:14:01 +08:00
af47e6bb88
Introduce an IP reset API for use on DaVinci SoC. There is no existing "reset" framework support for SoC devices. The remoteproc driver needs explicit control of the DSP's reset line. To support this, a new DaVinci specific API is added. This private API will disappear with DT migration. Some discussion regarding a proposed DT "reset" binding is here: https://patchwork.kernel.org/patch/1635051/ Modify davinci_clk_init() to set clk "reset" function for clocks that indicate PSC_LRST support. Also fix indentation issue with function opening curly brace. Signed-off-by: Robert Tivy <rtivy@ti.com> [nsekhar@ti.com: rename davinci_psc_config_reset() to davinci_psc_reset()] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
707 lines
15 KiB
C
707 lines
15 KiB
C
/*
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* Clock and PLL control for DaVinci devices
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*
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* Copyright (C) 2006-2007 Texas Instruments.
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* Copyright (C) 2008-2009 Deep Root Systems, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/mutex.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <mach/hardware.h>
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#include <mach/clock.h>
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#include <mach/psc.h>
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#include <mach/cputype.h>
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#include "clock.h"
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static LIST_HEAD(clocks);
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static DEFINE_MUTEX(clocks_mutex);
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static DEFINE_SPINLOCK(clockfw_lock);
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static void __clk_enable(struct clk *clk)
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{
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if (clk->parent)
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__clk_enable(clk->parent);
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if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
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davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
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true, clk->flags);
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}
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static void __clk_disable(struct clk *clk)
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{
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if (WARN_ON(clk->usecount == 0))
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return;
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if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
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(clk->flags & CLK_PSC))
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davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
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false, clk->flags);
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if (clk->parent)
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__clk_disable(clk->parent);
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}
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int davinci_clk_reset(struct clk *clk, bool reset)
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{
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unsigned long flags;
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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spin_lock_irqsave(&clockfw_lock, flags);
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if (clk->flags & CLK_PSC)
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davinci_psc_reset(clk->gpsc, clk->lpsc, reset);
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spin_unlock_irqrestore(&clockfw_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(davinci_clk_reset);
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int davinci_clk_reset_assert(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk) || !clk->reset)
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return -EINVAL;
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return clk->reset(clk, true);
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}
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EXPORT_SYMBOL(davinci_clk_reset_assert);
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int davinci_clk_reset_deassert(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk) || !clk->reset)
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return -EINVAL;
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return clk->reset(clk, false);
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}
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EXPORT_SYMBOL(davinci_clk_reset_deassert);
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int clk_enable(struct clk *clk)
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{
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unsigned long flags;
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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spin_lock_irqsave(&clockfw_lock, flags);
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__clk_enable(clk);
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spin_unlock_irqrestore(&clockfw_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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unsigned long flags;
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if (clk == NULL || IS_ERR(clk))
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return;
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spin_lock_irqsave(&clockfw_lock, flags);
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__clk_disable(clk);
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spin_unlock_irqrestore(&clockfw_lock, flags);
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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return clk->rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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long clk_round_rate(struct clk *clk, unsigned long rate)
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{
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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if (clk->round_rate)
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return clk->round_rate(clk, rate);
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return clk->rate;
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}
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EXPORT_SYMBOL(clk_round_rate);
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/* Propagate rate to children */
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static void propagate_rate(struct clk *root)
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{
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struct clk *clk;
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list_for_each_entry(clk, &root->children, childnode) {
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if (clk->recalc)
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clk->rate = clk->recalc(clk);
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propagate_rate(clk);
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}
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}
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long flags;
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int ret = -EINVAL;
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if (clk == NULL || IS_ERR(clk))
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return ret;
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if (clk->set_rate)
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ret = clk->set_rate(clk, rate);
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spin_lock_irqsave(&clockfw_lock, flags);
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if (ret == 0) {
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if (clk->recalc)
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clk->rate = clk->recalc(clk);
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propagate_rate(clk);
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}
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spin_unlock_irqrestore(&clockfw_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(clk_set_rate);
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int clk_set_parent(struct clk *clk, struct clk *parent)
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{
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unsigned long flags;
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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/* Cannot change parent on enabled clock */
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if (WARN_ON(clk->usecount))
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return -EINVAL;
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mutex_lock(&clocks_mutex);
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clk->parent = parent;
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list_del_init(&clk->childnode);
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list_add(&clk->childnode, &clk->parent->children);
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mutex_unlock(&clocks_mutex);
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spin_lock_irqsave(&clockfw_lock, flags);
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if (clk->recalc)
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clk->rate = clk->recalc(clk);
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propagate_rate(clk);
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spin_unlock_irqrestore(&clockfw_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(clk_set_parent);
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int clk_register(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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if (WARN(clk->parent && !clk->parent->rate,
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"CLK: %s parent %s has no rate!\n",
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clk->name, clk->parent->name))
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return -EINVAL;
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INIT_LIST_HEAD(&clk->children);
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mutex_lock(&clocks_mutex);
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list_add_tail(&clk->node, &clocks);
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if (clk->parent)
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list_add_tail(&clk->childnode, &clk->parent->children);
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mutex_unlock(&clocks_mutex);
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/* If rate is already set, use it */
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if (clk->rate)
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return 0;
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/* Else, see if there is a way to calculate it */
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if (clk->recalc)
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clk->rate = clk->recalc(clk);
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/* Otherwise, default to parent rate */
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else if (clk->parent)
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clk->rate = clk->parent->rate;
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return 0;
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}
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EXPORT_SYMBOL(clk_register);
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void clk_unregister(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk))
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return;
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mutex_lock(&clocks_mutex);
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list_del(&clk->node);
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list_del(&clk->childnode);
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mutex_unlock(&clocks_mutex);
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}
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EXPORT_SYMBOL(clk_unregister);
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#ifdef CONFIG_DAVINCI_RESET_CLOCKS
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/*
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* Disable any unused clocks left on by the bootloader
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*/
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int __init davinci_clk_disable_unused(void)
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{
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struct clk *ck;
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spin_lock_irq(&clockfw_lock);
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list_for_each_entry(ck, &clocks, node) {
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if (ck->usecount > 0)
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continue;
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if (!(ck->flags & CLK_PSC))
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continue;
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/* ignore if in Disabled or SwRstDisable states */
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if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc))
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continue;
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pr_debug("Clocks: disable unused %s\n", ck->name);
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davinci_psc_config(ck->domain, ck->gpsc, ck->lpsc,
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false, ck->flags);
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}
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spin_unlock_irq(&clockfw_lock);
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return 0;
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}
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#endif
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static unsigned long clk_sysclk_recalc(struct clk *clk)
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{
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u32 v, plldiv;
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struct pll_data *pll;
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unsigned long rate = clk->rate;
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/* If this is the PLL base clock, no more calculations needed */
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if (clk->pll_data)
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return rate;
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if (WARN_ON(!clk->parent))
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return rate;
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rate = clk->parent->rate;
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/* Otherwise, the parent must be a PLL */
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if (WARN_ON(!clk->parent->pll_data))
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return rate;
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pll = clk->parent->pll_data;
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/* If pre-PLL, source clock is before the multiplier and divider(s) */
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if (clk->flags & PRE_PLL)
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rate = pll->input_rate;
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if (!clk->div_reg)
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return rate;
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v = __raw_readl(pll->base + clk->div_reg);
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if (v & PLLDIV_EN) {
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plldiv = (v & pll->div_ratio_mask) + 1;
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if (plldiv)
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rate /= plldiv;
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}
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return rate;
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}
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int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
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{
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unsigned v;
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struct pll_data *pll;
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unsigned long input;
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unsigned ratio = 0;
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/* If this is the PLL base clock, wrong function to call */
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if (clk->pll_data)
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return -EINVAL;
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/* There must be a parent... */
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if (WARN_ON(!clk->parent))
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return -EINVAL;
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/* ... the parent must be a PLL... */
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if (WARN_ON(!clk->parent->pll_data))
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return -EINVAL;
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/* ... and this clock must have a divider. */
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if (WARN_ON(!clk->div_reg))
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return -EINVAL;
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pll = clk->parent->pll_data;
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input = clk->parent->rate;
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/* If pre-PLL, source clock is before the multiplier and divider(s) */
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if (clk->flags & PRE_PLL)
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input = pll->input_rate;
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if (input > rate) {
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/*
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* Can afford to provide an output little higher than requested
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* only if maximum rate supported by hardware on this sysclk
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* is known.
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*/
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if (clk->maxrate) {
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ratio = DIV_ROUND_CLOSEST(input, rate);
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if (input / ratio > clk->maxrate)
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ratio = 0;
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}
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if (ratio == 0)
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ratio = DIV_ROUND_UP(input, rate);
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ratio--;
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}
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if (ratio > pll->div_ratio_mask)
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return -EINVAL;
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do {
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v = __raw_readl(pll->base + PLLSTAT);
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} while (v & PLLSTAT_GOSTAT);
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v = __raw_readl(pll->base + clk->div_reg);
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v &= ~pll->div_ratio_mask;
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v |= ratio | PLLDIV_EN;
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__raw_writel(v, pll->base + clk->div_reg);
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v = __raw_readl(pll->base + PLLCMD);
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v |= PLLCMD_GOSET;
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__raw_writel(v, pll->base + PLLCMD);
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do {
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v = __raw_readl(pll->base + PLLSTAT);
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} while (v & PLLSTAT_GOSTAT);
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return 0;
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}
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EXPORT_SYMBOL(davinci_set_sysclk_rate);
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static unsigned long clk_leafclk_recalc(struct clk *clk)
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{
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if (WARN_ON(!clk->parent))
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return clk->rate;
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return clk->parent->rate;
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}
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int davinci_simple_set_rate(struct clk *clk, unsigned long rate)
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{
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clk->rate = rate;
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return 0;
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}
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static unsigned long clk_pllclk_recalc(struct clk *clk)
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{
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u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
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u8 bypass;
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struct pll_data *pll = clk->pll_data;
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unsigned long rate = clk->rate;
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ctrl = __raw_readl(pll->base + PLLCTL);
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rate = pll->input_rate = clk->parent->rate;
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if (ctrl & PLLCTL_PLLEN) {
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bypass = 0;
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mult = __raw_readl(pll->base + PLLM);
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if (cpu_is_davinci_dm365())
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mult = 2 * (mult & PLLM_PLLM_MASK);
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else
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mult = (mult & PLLM_PLLM_MASK) + 1;
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} else
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bypass = 1;
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if (pll->flags & PLL_HAS_PREDIV) {
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prediv = __raw_readl(pll->base + PREDIV);
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if (prediv & PLLDIV_EN)
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prediv = (prediv & pll->div_ratio_mask) + 1;
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else
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prediv = 1;
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}
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/* pre-divider is fixed, but (some?) chips won't report that */
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if (cpu_is_davinci_dm355() && pll->num == 1)
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prediv = 8;
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if (pll->flags & PLL_HAS_POSTDIV) {
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postdiv = __raw_readl(pll->base + POSTDIV);
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if (postdiv & PLLDIV_EN)
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postdiv = (postdiv & pll->div_ratio_mask) + 1;
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else
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postdiv = 1;
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}
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if (!bypass) {
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rate /= prediv;
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rate *= mult;
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rate /= postdiv;
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}
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pr_debug("PLL%d: input = %lu MHz [ ",
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pll->num, clk->parent->rate / 1000000);
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if (bypass)
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pr_debug("bypass ");
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if (prediv > 1)
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pr_debug("/ %d ", prediv);
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if (mult > 1)
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pr_debug("* %d ", mult);
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if (postdiv > 1)
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pr_debug("/ %d ", postdiv);
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pr_debug("] --> %lu MHz output.\n", rate / 1000000);
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return rate;
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}
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/**
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* davinci_set_pllrate - set the output rate of a given PLL.
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*
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* Note: Currently tested to work with OMAP-L138 only.
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*
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* @pll: pll whose rate needs to be changed.
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* @prediv: The pre divider value. Passing 0 disables the pre-divider.
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* @pllm: The multiplier value. Passing 0 leads to multiply-by-one.
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* @postdiv: The post divider value. Passing 0 disables the post-divider.
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*/
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int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
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unsigned int mult, unsigned int postdiv)
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{
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u32 ctrl;
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unsigned int locktime;
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unsigned long flags;
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if (pll->base == NULL)
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return -EINVAL;
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/*
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* PLL lock time required per OMAP-L138 datasheet is
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* (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm)
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* as 4 and OSCIN cycle as 25 MHz.
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*/
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if (prediv) {
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locktime = ((2000 * prediv) / 100);
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prediv = (prediv - 1) | PLLDIV_EN;
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} else {
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locktime = PLL_LOCK_TIME;
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}
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if (postdiv)
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postdiv = (postdiv - 1) | PLLDIV_EN;
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if (mult)
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mult = mult - 1;
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/* Protect against simultaneous calls to PLL setting seqeunce */
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spin_lock_irqsave(&clockfw_lock, flags);
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ctrl = __raw_readl(pll->base + PLLCTL);
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/* Switch the PLL to bypass mode */
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ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
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__raw_writel(ctrl, pll->base + PLLCTL);
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udelay(PLL_BYPASS_TIME);
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/* Reset and enable PLL */
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ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
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__raw_writel(ctrl, pll->base + PLLCTL);
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if (pll->flags & PLL_HAS_PREDIV)
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__raw_writel(prediv, pll->base + PREDIV);
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__raw_writel(mult, pll->base + PLLM);
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if (pll->flags & PLL_HAS_POSTDIV)
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__raw_writel(postdiv, pll->base + POSTDIV);
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udelay(PLL_RESET_TIME);
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/* Bring PLL out of reset */
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ctrl |= PLLCTL_PLLRST;
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__raw_writel(ctrl, pll->base + PLLCTL);
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udelay(locktime);
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/* Remove PLL from bypass mode */
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ctrl |= PLLCTL_PLLEN;
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__raw_writel(ctrl, pll->base + PLLCTL);
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spin_unlock_irqrestore(&clockfw_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(davinci_set_pllrate);
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/**
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* davinci_set_refclk_rate() - Set the reference clock rate
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* @rate: The new rate.
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*
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* Sets the reference clock rate to a given value. This will most likely
|
|
* result in the entire clock tree getting updated.
|
|
*
|
|
* This is used to support boards which use a reference clock different
|
|
* than that used by default in <soc>.c file. The reference clock rate
|
|
* should be updated early in the boot process; ideally soon after the
|
|
* clock tree has been initialized once with the default reference clock
|
|
* rate (davinci_common_init()).
|
|
*
|
|
* Returns 0 on success, error otherwise.
|
|
*/
|
|
int davinci_set_refclk_rate(unsigned long rate)
|
|
{
|
|
struct clk *refclk;
|
|
|
|
refclk = clk_get(NULL, "ref");
|
|
if (IS_ERR(refclk)) {
|
|
pr_err("%s: failed to get reference clock.\n", __func__);
|
|
return PTR_ERR(refclk);
|
|
}
|
|
|
|
clk_set_rate(refclk, rate);
|
|
|
|
clk_put(refclk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int __init davinci_clk_init(struct clk_lookup *clocks)
|
|
{
|
|
struct clk_lookup *c;
|
|
struct clk *clk;
|
|
size_t num_clocks = 0;
|
|
|
|
for (c = clocks; c->clk; c++) {
|
|
clk = c->clk;
|
|
|
|
if (!clk->recalc) {
|
|
|
|
/* Check if clock is a PLL */
|
|
if (clk->pll_data)
|
|
clk->recalc = clk_pllclk_recalc;
|
|
|
|
/* Else, if it is a PLL-derived clock */
|
|
else if (clk->flags & CLK_PLL)
|
|
clk->recalc = clk_sysclk_recalc;
|
|
|
|
/* Otherwise, it is a leaf clock (PSC clock) */
|
|
else if (clk->parent)
|
|
clk->recalc = clk_leafclk_recalc;
|
|
}
|
|
|
|
if (clk->pll_data) {
|
|
struct pll_data *pll = clk->pll_data;
|
|
|
|
if (!pll->div_ratio_mask)
|
|
pll->div_ratio_mask = PLLDIV_RATIO_MASK;
|
|
|
|
if (pll->phys_base && !pll->base) {
|
|
pll->base = ioremap(pll->phys_base, SZ_4K);
|
|
WARN_ON(!pll->base);
|
|
}
|
|
}
|
|
|
|
if (clk->recalc)
|
|
clk->rate = clk->recalc(clk);
|
|
|
|
if (clk->lpsc)
|
|
clk->flags |= CLK_PSC;
|
|
|
|
if (clk->flags & PSC_LRST)
|
|
clk->reset = davinci_clk_reset;
|
|
|
|
clk_register(clk);
|
|
num_clocks++;
|
|
|
|
/* Turn on clocks that Linux doesn't otherwise manage */
|
|
if (clk->flags & ALWAYS_ENABLED)
|
|
clk_enable(clk);
|
|
}
|
|
|
|
clkdev_add_table(clocks, num_clocks);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
|
|
#include <linux/debugfs.h>
|
|
#include <linux/seq_file.h>
|
|
|
|
#define CLKNAME_MAX 10 /* longest clock name */
|
|
#define NEST_DELTA 2
|
|
#define NEST_MAX 4
|
|
|
|
static void
|
|
dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
|
|
{
|
|
char *state;
|
|
char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
|
|
struct clk *clk;
|
|
unsigned i;
|
|
|
|
if (parent->flags & CLK_PLL)
|
|
state = "pll";
|
|
else if (parent->flags & CLK_PSC)
|
|
state = "psc";
|
|
else
|
|
state = "";
|
|
|
|
/* <nest spaces> name <pad to end> */
|
|
memset(buf, ' ', sizeof(buf) - 1);
|
|
buf[sizeof(buf) - 1] = 0;
|
|
i = strlen(parent->name);
|
|
memcpy(buf + nest, parent->name,
|
|
min(i, (unsigned)(sizeof(buf) - 1 - nest)));
|
|
|
|
seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
|
|
buf, parent->usecount, state, clk_get_rate(parent));
|
|
/* REVISIT show device associations too */
|
|
|
|
/* cost is now small, but not linear... */
|
|
list_for_each_entry(clk, &parent->children, childnode) {
|
|
dump_clock(s, nest + NEST_DELTA, clk);
|
|
}
|
|
}
|
|
|
|
static int davinci_ck_show(struct seq_file *m, void *v)
|
|
{
|
|
struct clk *clk;
|
|
|
|
/*
|
|
* Show clock tree; We trust nonzero usecounts equate to PSC enables...
|
|
*/
|
|
mutex_lock(&clocks_mutex);
|
|
list_for_each_entry(clk, &clocks, node)
|
|
if (!clk->parent)
|
|
dump_clock(m, 0, clk);
|
|
mutex_unlock(&clocks_mutex);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int davinci_ck_open(struct inode *inode, struct file *file)
|
|
{
|
|
return single_open(file, davinci_ck_show, NULL);
|
|
}
|
|
|
|
static const struct file_operations davinci_ck_operations = {
|
|
.open = davinci_ck_open,
|
|
.read = seq_read,
|
|
.llseek = seq_lseek,
|
|
.release = single_release,
|
|
};
|
|
|
|
static int __init davinci_clk_debugfs_init(void)
|
|
{
|
|
debugfs_create_file("davinci_clocks", S_IFREG | S_IRUGO, NULL, NULL,
|
|
&davinci_ck_operations);
|
|
return 0;
|
|
|
|
}
|
|
device_initcall(davinci_clk_debugfs_init);
|
|
#endif /* CONFIG_DEBUG_FS */
|