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ed3593f986
all-caps node name is not very usual. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
57 lines
1.2 KiB
Plaintext
57 lines
1.2 KiB
Plaintext
/*
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* Copyright (C) 2013 STMicroelectronics R&D Limited
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* <stlinux-devel@stlinux.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/ {
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clocks {
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/*
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* Fixed 30MHz oscillator inputs to SoC
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*/
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clk_sysin: clk-sysin {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <30000000>;
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};
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/*
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* ARM Peripheral clock for timers
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*/
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arm_periph_clk: arm_periph_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <600000000>;
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};
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/*
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* Bootloader initialized system infrastructure clock for
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* serial devices.
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*/
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CLK_S_ICN_REG_0: clockgenA0@4 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <100000000>;
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clock-output-names = "CLK_S_ICN_REG_0";
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};
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CLK_S_GMAC0_PHY: clockgenA1@7 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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clock-output-names = "CLK_S_GMAC0_PHY";
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};
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CLK_S_ETH1_PHY: clockgenA0@7 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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clock-output-names = "CLK_S_ETH1_PHY";
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};
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};
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};
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