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5d60e50054
The accessibility checking method to the higher register was added by
69d1fe18e9 (mmc: tmio: only access registers above 0xff, if available)
But, it doesn't care 32bit register. It is impossible to calculate it
from the resource size, since there is 16/32 bit register IP (e.g. VERSION
is located on 0xe2 if 16bit register, but it is located on 0x1c4 if 32bit
register).
This patch adds new TMIO_MMC_HAVE_HIGH_REG flags, tmio_mmc driver has it,
and sh_mobile_sdhi doesn't have it today.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
152 lines
4.2 KiB
C
152 lines
4.2 KiB
C
#ifndef MFD_TMIO_H
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#define MFD_TMIO_H
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#include <linux/device.h>
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#include <linux/fb.h>
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#include <linux/io.h>
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#include <linux/jiffies.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#define tmio_ioread8(addr) readb(addr)
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#define tmio_ioread16(addr) readw(addr)
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#define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
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#define tmio_ioread32(addr) \
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(((u32) readw((addr))) | (((u32) readw((addr) + 2)) << 16))
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#define tmio_iowrite8(val, addr) writeb((val), (addr))
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#define tmio_iowrite16(val, addr) writew((val), (addr))
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#define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
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#define tmio_iowrite32(val, addr) \
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do { \
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writew((val), (addr)); \
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writew((val) >> 16, (addr) + 2); \
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} while (0)
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#define CNF_CMD 0x04
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#define CNF_CTL_BASE 0x10
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#define CNF_INT_PIN 0x3d
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#define CNF_STOP_CLK_CTL 0x40
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#define CNF_GCLK_CTL 0x41
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#define CNF_SD_CLK_MODE 0x42
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#define CNF_PIN_STATUS 0x44
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#define CNF_PWR_CTL_1 0x48
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#define CNF_PWR_CTL_2 0x49
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#define CNF_PWR_CTL_3 0x4a
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#define CNF_CARD_DETECT_MODE 0x4c
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#define CNF_SD_SLOT 0x50
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#define CNF_EXT_GCLK_CTL_1 0xf0
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#define CNF_EXT_GCLK_CTL_2 0xf1
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#define CNF_EXT_GCLK_CTL_3 0xf9
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#define CNF_SD_LED_EN_1 0xfa
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#define CNF_SD_LED_EN_2 0xfe
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#define SDCREN 0x2 /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/
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#define sd_config_write8(base, shift, reg, val) \
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tmio_iowrite8((val), (base) + ((reg) << (shift)))
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#define sd_config_write16(base, shift, reg, val) \
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tmio_iowrite16((val), (base) + ((reg) << (shift)))
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#define sd_config_write32(base, shift, reg, val) \
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do { \
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tmio_iowrite16((val), (base) + ((reg) << (shift))); \
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tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
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} while (0)
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/* tmio MMC platform flags */
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#define TMIO_MMC_WRPROTECT_DISABLE (1 << 0)
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/*
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* Some controllers can support a 2-byte block size when the bus width
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* is configured in 4-bit mode.
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*/
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#define TMIO_MMC_BLKSZ_2BYTES (1 << 1)
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/*
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* Some controllers can support SDIO IRQ signalling.
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*/
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#define TMIO_MMC_SDIO_IRQ (1 << 2)
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/*
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* Some controllers require waiting for the SD bus to become
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* idle before writing to some registers.
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*/
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#define TMIO_MMC_HAS_IDLE_WAIT (1 << 4)
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/*
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* A GPIO is used for card hotplug detection. We need an extra flag for this,
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* because 0 is a valid GPIO number too, and requiring users to specify
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* cd_gpio < 0 to disable GPIO hotplug would break backwards compatibility.
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*/
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#define TMIO_MMC_USE_GPIO_CD (1 << 5)
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/*
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* Some controllers doesn't have over 0x100 register.
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* it is used to checking accessibility of
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* CTL_SD_CARD_CLK_CTL / CTL_CLK_AND_WAIT_CTL
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*/
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#define TMIO_MMC_HAVE_HIGH_REG (1 << 6)
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int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
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int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
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void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
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void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
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struct dma_chan;
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struct tmio_mmc_dma {
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void *chan_priv_tx;
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void *chan_priv_rx;
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int slave_id_tx;
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int slave_id_rx;
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int alignment_shift;
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bool (*filter)(struct dma_chan *chan, void *arg);
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};
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struct tmio_mmc_host;
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/*
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* data for the MMC controller
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*/
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struct tmio_mmc_data {
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unsigned int hclk;
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unsigned long capabilities;
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unsigned long capabilities2;
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unsigned long flags;
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unsigned long bus_shift;
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u32 ocr_mask; /* available voltages */
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struct tmio_mmc_dma *dma;
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struct device *dev;
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unsigned int cd_gpio;
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void (*set_pwr)(struct platform_device *host, int state);
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void (*set_clk_div)(struct platform_device *host, int state);
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int (*write16_hook)(struct tmio_mmc_host *host, int addr);
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/* clock management callbacks */
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int (*clk_enable)(struct platform_device *pdev, unsigned int *f);
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void (*clk_disable)(struct platform_device *pdev);
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};
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/*
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* data for the NAND controller
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*/
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struct tmio_nand_data {
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struct nand_bbt_descr *badblock_pattern;
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struct mtd_partition *partition;
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unsigned int num_partitions;
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};
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#define FBIO_TMIO_ACC_WRITE 0x7C639300
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#define FBIO_TMIO_ACC_SYNC 0x7C639301
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struct tmio_fb_data {
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int (*lcd_set_power)(struct platform_device *fb_dev,
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bool on);
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int (*lcd_mode)(struct platform_device *fb_dev,
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const struct fb_videomode *mode);
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int num_modes;
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struct fb_videomode *modes;
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/* in mm: size of screen */
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int height;
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int width;
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};
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#endif
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