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078a55fc82
commit 3747069b25e419f6b51395f48127e9812abc3596 upstream.
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.
Here, we remove all the MIPS __cpuinit from C code and __CPUINIT
from asm files. MIPS is interesting in this respect, because there
are also uasm users hiding behind their own renamed versions of the
__cpuinit macros.
[1] https://lkml.org/lkml/2013/5/20/589
[ralf@linux-mips.org: Folded in Paul's followup fix.]
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5494/
Patchwork: https://patchwork.linux-mips.org/patch/5495/
Patchwork: https://patchwork.linux-mips.org/patch/5509/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
144 lines
3.2 KiB
C
144 lines
3.2 KiB
C
/*
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* Copyright (C) 2006 Chris Dearman (chris@mips.com),
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <asm/mipsregs.h>
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#include <asm/bcache.h>
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#include <asm/cacheops.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/mmu_context.h>
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#include <asm/r4kcache.h>
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/*
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* MIPS32/MIPS64 L2 cache handling
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*/
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/*
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* Writeback and invalidate the secondary cache before DMA.
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*/
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static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
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{
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blast_scache_range(addr, addr + size);
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}
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/*
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* Invalidate the secondary cache before DMA.
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*/
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static void mips_sc_inv(unsigned long addr, unsigned long size)
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{
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unsigned long lsize = cpu_scache_line_size();
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unsigned long almask = ~(lsize - 1);
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cache_op(Hit_Writeback_Inv_SD, addr & almask);
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cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
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blast_inv_scache_range(addr, addr + size);
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}
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static void mips_sc_enable(void)
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{
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/* L2 cache is permanently enabled */
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}
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static void mips_sc_disable(void)
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{
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/* L2 cache is permanently enabled */
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}
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static struct bcache_ops mips_sc_ops = {
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.bc_enable = mips_sc_enable,
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.bc_disable = mips_sc_disable,
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.bc_wback_inv = mips_sc_wback_inv,
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.bc_inv = mips_sc_inv
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};
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/*
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* Check if the L2 cache controller is activated on a particular platform.
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* MTI's L2 controller and the L2 cache controller of Broadcom's BMIPS
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* cores both use c0_config2's bit 12 as "L2 Bypass" bit, that is the
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* cache being disabled. However there is no guarantee for this to be
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* true on all platforms. In an act of stupidity the spec defined bits
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* 12..15 as implementation defined so below function will eventually have
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* to be replaced by a platform specific probe.
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*/
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static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
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{
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unsigned int config2 = read_c0_config2();
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unsigned int tmp;
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/* Check the bypass bit (L2B) */
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switch (c->cputype) {
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case CPU_34K:
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case CPU_74K:
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case CPU_1004K:
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case CPU_BMIPS5000:
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if (config2 & (1 << 12))
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return 0;
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}
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tmp = (config2 >> 4) & 0x0f;
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if (0 < tmp && tmp <= 7)
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c->scache.linesz = 2 << tmp;
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else
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return 0;
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return 1;
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}
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static inline int __init mips_sc_probe(void)
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{
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struct cpuinfo_mips *c = ¤t_cpu_data;
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unsigned int config1, config2;
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unsigned int tmp;
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/* Mark as not present until probe completed */
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c->scache.flags |= MIPS_CACHE_NOT_PRESENT;
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/* Ignore anything but MIPSxx processors */
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if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
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MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)))
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return 0;
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/* Does this MIPS32/MIPS64 CPU have a config2 register? */
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config1 = read_c0_config1();
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if (!(config1 & MIPS_CONF_M))
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return 0;
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config2 = read_c0_config2();
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if (!mips_sc_is_activated(c))
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return 0;
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tmp = (config2 >> 8) & 0x0f;
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if (0 <= tmp && tmp <= 7)
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c->scache.sets = 64 << tmp;
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else
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return 0;
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tmp = (config2 >> 0) & 0x0f;
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if (0 <= tmp && tmp <= 7)
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c->scache.ways = tmp + 1;
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else
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return 0;
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c->scache.waysize = c->scache.sets * c->scache.linesz;
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c->scache.waybit = __ffs(c->scache.waysize);
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c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
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return 1;
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}
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int mips_sc_init(void)
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{
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int found = mips_sc_probe();
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if (found) {
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mips_sc_enable();
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bcops = &mips_sc_ops;
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}
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return found;
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}
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