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This describes a compatible entry of the form: ethernet-phy-idAAAA,BBBB Which is modelled after the PCI structured compatible entry (pciVVVV,DDDD.SSSS.ssss.RR) If present the OF core will be able to use this information to directly create the correct phy without auto probing the bus. Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
40 lines
1.5 KiB
Plaintext
40 lines
1.5 KiB
Plaintext
PHY nodes
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Required properties:
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- interrupts : <a b> where a is the interrupt number and b is a
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field that represents an encoding of the sense and level
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information for the interrupt. This should be encoded based on
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the information in section 2) depending on the type of interrupt
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controller you have.
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- interrupt-parent : the phandle for the interrupt controller that
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services interrupts for this device.
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- reg : The ID number for the phy, usually a small integer
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Optional Properties:
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- compatible: Compatible list, may contain
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"ethernet-phy-ieee802.3-c22" or "ethernet-phy-ieee802.3-c45" for
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PHYs that implement IEEE802.3 clause 22 or IEEE802.3 clause 45
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specifications. If neither of these are specified, the default is to
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assume clause 22. The compatible list may also contain other
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elements.
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- max-speed: Maximum PHY supported speed (10, 100, 1000...)
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If the phy's identifier is known then the list may contain an entry
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of the form: "ethernet-phy-idAAAA.BBBB" where
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AAAA - The value of the 16 bit Phy Identifier 1 register as
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4 hex digits. This is the chip vendor OUI bits 3:18
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BBBB - The value of the 16 bit Phy Identifier 2 register as
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4 hex digits. This is the chip vendor OUI bits 19:24,
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followed by 10 bits of a vendor specific ID.
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Example:
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ethernet-phy@0 {
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compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c22";
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interrupt-parent = <40000>;
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interrupts = <35 1>;
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reg = <0>;
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};
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