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This driver allows to provide DT clocks for core clocks found on Marvell Kirkwood, Dove & 370/XP SoCs. The core clock frequencies and ratios are determined by decoding the Sample-At-Reset registers. Although technically correct, using a divider of 0 will lead to div_by_zero panic. Let's use a ratio of 0/1 instead to fail later with a zero clock. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by Gregory CLEMENT <gregory.clement@free-electrons.com>
48 lines
1.6 KiB
Plaintext
48 lines
1.6 KiB
Plaintext
* Core Clock bindings for Marvell MVEBU SoCs
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Marvell MVEBU SoCs usually allow to determine core clock frequencies by
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reading the Sample-At-Reset (SAR) register. The core clock consumer should
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specify the desired clock by having the clock ID in its "clocks" phandle cell.
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The following is a list of provided IDs and clock names on Armada 370/XP:
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU clock)
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2 = nbclk (L2 Cache clock)
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3 = hclk (DRAM control clock)
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4 = dramclk (DDR clock)
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The following is a list of provided IDs and clock names on Kirkwood and Dove:
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU0 clock)
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2 = l2clk (L2 Cache clock derived from CPU0 clock)
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3 = ddrclk (DDR controller clock derived from CPU0 clock)
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Required properties:
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- compatible : shall be one of the following:
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"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
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"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
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"marvell,dove-core-clock" - for Dove SoC core clocks
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"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
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"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
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- reg : shall be the register address of the Sample-At-Reset (SAR) register
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- #clock-cells : from common clock binding; shall be set to 1
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Optional properties:
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- clock-output-names : from common clock binding; allows overwrite default clock
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output names ("tclk", "cpuclk", "l2clk", "ddrclk")
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Example:
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core_clk: core-clocks@d0214 {
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compatible = "marvell,dove-core-clock";
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reg = <0xd0214 0x4>;
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#clock-cells = <1>;
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};
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spi0: spi@10600 {
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compatible = "marvell,orion-spi";
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/* ... */
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/* get tclk from core clock provider */
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clocks = <&core_clk 0>;
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};
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