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ea0f8feaa0
The following moves the creation of IPR interupts into setup-7750.c and updates a few other things to make it all work after the "Drop CPU subtype IRQ headers" commit. It boots and runs fine on my titan board. - adds an ipr_idx to the ipr_data and uses a function in the subtype code to calculate the address of the IPR registers - adds a function to enable individual interrupt mode for externals in the subtype code and calls that from the titan board code instead of doing it directly. - I changed the shift in the ipr_data to be the actual # of bits to shift, instead of the numnber / 4 - made it easier to match with the manual. Signed-off-by: Jamie Lenehan <lenehan@twibble.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org> |
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| .. | ||
| cache-debugfs.c | ||
| cache-sh2.c | ||
| cache-sh3.c | ||
| cache-sh4.c | ||
| cache-sh7705.c | ||
| clear_page.S | ||
| consistent.c | ||
| copy_page.S | ||
| extable.c | ||
| fault-nommu.c | ||
| fault.c | ||
| hugetlbpage.c | ||
| init.c | ||
| ioremap.c | ||
| Kconfig | ||
| Makefile | ||
| pg-dma.c | ||
| pg-nommu.c | ||
| pg-sh4.c | ||
| pg-sh7705.c | ||
| pmb.c | ||
| tlb-flush.c | ||
| tlb-nommu.c | ||
| tlb-sh3.c | ||
| tlb-sh4.c | ||