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ef6edc9746
On systems running with virtual cpus there is optimization potential in regard to spinlocks and rw-locks. If the virtual cpu that has taken a lock is known to a cpu that wants to acquire the same lock it is beneficial to yield the timeslice of the virtual cpu in favour of the cpu that has the lock (directed yield). With CONFIG_PREEMPT="n" this can be implemented by the architecture without common code changes. Powerpc already does this. With CONFIG_PREEMPT="y" the lock loops are coded with _raw_spin_trylock, _raw_read_trylock and _raw_write_trylock in kernel/spinlock.c. If the lock could not be taken cpu_relax is called. A directed yield is not possible because cpu_relax doesn't know anything about the lock. To be able to yield the lock in favour of the current lock holder variants of cpu_relax for spinlocks and rw-locks are needed. The new _raw_spin_relax, _raw_read_relax and _raw_write_relax primitives differ from cpu_relax insofar that they have an argument: a pointer to the lock structure. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Paul Mackerras <paulus@samba.org> Cc: Haavard Skinnemoen <hskinnemoen@atmel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
226 lines
4.3 KiB
C
226 lines
4.3 KiB
C
#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#if __LINUX_ARM_ARCH__ < 6
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#error SMP not supported on pre-ARMv6 CPUs
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#endif
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/*
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* ARMv6 Spin-locking.
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*
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* We exclusively read the old value. If it is zero, we may have
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* won the lock, so we try exclusively storing it. A memory barrier
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* is required after we get a lock, and before we release it, because
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* V6 CPUs are assumed to have weakly ordered memory.
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*
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* Unlocked value: 0
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* Locked value: 1
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*/
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#define __raw_spin_is_locked(x) ((x)->lock != 0)
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#define __raw_spin_unlock_wait(lock) \
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do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
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#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
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static inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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"1: ldrex %0, [%1]\n"
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" teq %0, #0\n"
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#ifdef CONFIG_CPU_32v6K
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" wfene\n"
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#endif
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" strexeq %0, %2, [%1]\n"
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" teqeq %0, #0\n"
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" bne 1b"
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: "=&r" (tmp)
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: "r" (&lock->lock), "r" (1)
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: "cc");
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smp_mb();
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}
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static inline int __raw_spin_trylock(raw_spinlock_t *lock)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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" ldrex %0, [%1]\n"
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" teq %0, #0\n"
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" strexeq %0, %2, [%1]"
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: "=&r" (tmp)
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: "r" (&lock->lock), "r" (1)
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: "cc");
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if (tmp == 0) {
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smp_mb();
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return 1;
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} else {
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return 0;
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}
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}
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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smp_mb();
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__asm__ __volatile__(
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" str %1, [%0]\n"
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#ifdef CONFIG_CPU_32v6K
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" mcr p15, 0, %1, c7, c10, 4\n" /* DSB */
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" sev"
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#endif
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:
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: "r" (&lock->lock), "r" (0)
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: "cc");
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}
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/*
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* RWLOCKS
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*
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*
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* Write locks are easy - we just set bit 31. When unlocking, we can
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* just write zero since the lock is exclusively held.
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*/
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#define rwlock_is_locked(x) (*((volatile unsigned int *)(x)) != 0)
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static inline void __raw_write_lock(raw_rwlock_t *rw)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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"1: ldrex %0, [%1]\n"
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" teq %0, #0\n"
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#ifdef CONFIG_CPU_32v6K
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" wfene\n"
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#endif
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" strexeq %0, %2, [%1]\n"
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" teq %0, #0\n"
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" bne 1b"
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: "=&r" (tmp)
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: "r" (&rw->lock), "r" (0x80000000)
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: "cc");
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smp_mb();
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}
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static inline int __raw_write_trylock(raw_rwlock_t *rw)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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"1: ldrex %0, [%1]\n"
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" teq %0, #0\n"
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" strexeq %0, %2, [%1]"
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: "=&r" (tmp)
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: "r" (&rw->lock), "r" (0x80000000)
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: "cc");
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if (tmp == 0) {
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smp_mb();
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return 1;
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} else {
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return 0;
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}
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}
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static inline void __raw_write_unlock(raw_rwlock_t *rw)
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{
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smp_mb();
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__asm__ __volatile__(
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"str %1, [%0]\n"
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#ifdef CONFIG_CPU_32v6K
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" mcr p15, 0, %1, c7, c10, 4\n" /* DSB */
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" sev\n"
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#endif
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:
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: "r" (&rw->lock), "r" (0)
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: "cc");
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}
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/* write_can_lock - would write_trylock() succeed? */
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#define __raw_write_can_lock(x) ((x)->lock == 0x80000000)
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/*
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* Read locks are a bit more hairy:
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* - Exclusively load the lock value.
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* - Increment it.
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* - Store new lock value if positive, and we still own this location.
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* If the value is negative, we've already failed.
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* - If we failed to store the value, we want a negative result.
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* - If we failed, try again.
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* Unlocking is similarly hairy. We may have multiple read locks
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* currently active. However, we know we won't have any write
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* locks.
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*/
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static inline void __raw_read_lock(raw_rwlock_t *rw)
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{
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unsigned long tmp, tmp2;
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__asm__ __volatile__(
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"1: ldrex %0, [%2]\n"
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" adds %0, %0, #1\n"
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" strexpl %1, %0, [%2]\n"
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#ifdef CONFIG_CPU_32v6K
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" wfemi\n"
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#endif
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" rsbpls %0, %1, #0\n"
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" bmi 1b"
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: "=&r" (tmp), "=&r" (tmp2)
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: "r" (&rw->lock)
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: "cc");
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smp_mb();
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}
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static inline void __raw_read_unlock(raw_rwlock_t *rw)
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{
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unsigned long tmp, tmp2;
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smp_mb();
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__asm__ __volatile__(
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"1: ldrex %0, [%2]\n"
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" sub %0, %0, #1\n"
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" strex %1, %0, [%2]\n"
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" teq %1, #0\n"
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" bne 1b"
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#ifdef CONFIG_CPU_32v6K
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"\n cmp %0, #0\n"
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" mcreq p15, 0, %0, c7, c10, 4\n"
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" seveq"
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#endif
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: "=&r" (tmp), "=&r" (tmp2)
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: "r" (&rw->lock)
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: "cc");
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}
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static inline int __raw_read_trylock(raw_rwlock_t *rw)
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{
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unsigned long tmp, tmp2 = 1;
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__asm__ __volatile__(
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"1: ldrex %0, [%2]\n"
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" adds %0, %0, #1\n"
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" strexpl %1, %0, [%2]\n"
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: "=&r" (tmp), "+r" (tmp2)
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: "r" (&rw->lock)
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: "cc");
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smp_mb();
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return tmp2 == 0;
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}
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/* read_can_lock - would read_trylock() succeed? */
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#define __raw_read_can_lock(x) ((x)->lock < 0x80000000)
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#define _raw_spin_relax(lock) cpu_relax()
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#define _raw_read_relax(lock) cpu_relax()
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#define _raw_write_relax(lock) cpu_relax()
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#endif /* __ASM_SPINLOCK_H */
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