Nicolas Pitre e8f9bb1bd6 ARM: vexpress/dcscb: fix cache disabling sequences ... Unlike real A15/A7's, the RTSM simulation doesn't appear to hit the cache when the CTRL.C bit is cleared. Let's ensure there is no memory access within the disable and flush cache sequence, including to the stack. Signed-off-by: Nicolas Pitre <nico@linaro.org>		2013-07-22 12:26:09 -04:00
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include/mach	ARM: vexpress: Start using new Versatile Express infrastructure	2012-11-05 17:09:51 +00:00
core.h	ARM: vexpress: Select multi-cluster SMP operation if required	2013-05-29 15:50:35 -04:00
ct-ca9x4.c	irqchip: Move ARM gic.h to include/linux/irqchip/arm-gic.h	2013-01-12 10:47:32 -06:00
dcscb_setup.S	ARM: vexpress/dcscb: handle platform coherency exit/setup and CCI	2013-05-29 15:50:35 -04:00
dcscb.c	ARM: vexpress/dcscb: fix cache disabling sequences	2013-07-22 12:26:09 -04:00
hotplug.c	ARM: cpu hotplug: remove majority of cache flushing from platforms	2013-04-18 20:08:04 +01:00
Kconfig	ARM: vexpress/dcscb: handle platform coherency exit/setup and CCI	2013-05-29 15:50:35 -04:00
Makefile	ARM: vexpress/dcscb: handle platform coherency exit/setup and CCI	2013-05-29 15:50:35 -04:00
platsmp.c	ARM: vexpress: Select multi-cluster SMP operation if required	2013-05-29 15:50:35 -04:00
v2m.c	ARM SoC specific changes	2013-07-02 13:43:38 -07:00