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df5c7386f6
Provide a flag to choose if the device does support memory-to-memory transfers. At least this is not true for iDMA32 controller that might be supported in the future. Besides that Intel BayTrail and Braswell users should not try this feature due to HW specific behaviour. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
64 lines
2.1 KiB
C
64 lines
2.1 KiB
C
/*
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* Driver for the Synopsys DesignWare DMA Controller
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*
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* Copyright (C) 2007 Atmel Corporation
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* Copyright (C) 2010-2011 ST Microelectronics
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _PLATFORM_DATA_DMA_DW_H
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#define _PLATFORM_DATA_DMA_DW_H
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#include <linux/device.h>
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#define DW_DMA_MAX_NR_MASTERS 4
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/**
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* struct dw_dma_slave - Controller-specific information about a slave
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*
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* @dma_dev: required DMA master device
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* @src_id: src request line
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* @dst_id: dst request line
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* @src_master: src master for transfers on allocated channel.
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* @dst_master: dest master for transfers on allocated channel.
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*/
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struct dw_dma_slave {
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struct device *dma_dev;
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u8 src_id;
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u8 dst_id;
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u8 src_master;
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u8 dst_master;
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};
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/**
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* struct dw_dma_platform_data - Controller configuration parameters
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* @nr_channels: Number of channels supported by hardware (max 8)
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* @is_private: The device channels should be marked as private and not for
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* by the general purpose DMA channel allocator.
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* @is_memcpy: The device channels do support memory-to-memory transfers.
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* @chan_allocation_order: Allocate channels starting from 0 or 7
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* @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
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* @block_size: Maximum block size supported by the controller
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* @nr_masters: Number of AHB masters supported by the controller
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* @data_width: Maximum data width supported by hardware per AHB master
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* (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
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*/
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struct dw_dma_platform_data {
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unsigned int nr_channels;
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bool is_private;
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bool is_memcpy;
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#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
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#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
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unsigned char chan_allocation_order;
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#define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */
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#define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */
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unsigned char chan_priority;
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unsigned short block_size;
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unsigned char nr_masters;
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unsigned char data_width[DW_DMA_MAX_NR_MASTERS];
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};
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#endif /* _PLATFORM_DATA_DMA_DW_H */
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