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e7eacd3686
Signed-off-by: Ralph Campbell <ralph.campbell@qlogic.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
1184 lines
30 KiB
C
1184 lines
30 KiB
C
/*
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* Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
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* Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/vmalloc.h>
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#include "ipath_kernel.h"
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/*
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* InfiniPath I2C driver for a serial eeprom. This is not a generic
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* I2C interface. For a start, the device we're using (Atmel AT24C11)
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* doesn't work like a regular I2C device. It looks like one
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* electrically, but not logically. Normal I2C devices have a single
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* 7-bit or 10-bit I2C address that they respond to. Valid 7-bit
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* addresses range from 0x03 to 0x77. Addresses 0x00 to 0x02 and 0x78
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* to 0x7F are special reserved addresses (e.g. 0x00 is the "general
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* call" address.) The Atmel device, on the other hand, responds to ALL
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* 7-bit addresses. It's designed to be the only device on a given I2C
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* bus. A 7-bit address corresponds to the memory address within the
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* Atmel device itself.
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*
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* Also, the timing requirements mean more than simple software
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* bitbanging, with readbacks from chip to ensure timing (simple udelay
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* is not enough).
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*
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* This all means that accessing the device is specialized enough
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* that using the standard kernel I2C bitbanging interface would be
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* impossible. For example, the core I2C eeprom driver expects to find
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* a device at one or more of a limited set of addresses only. It doesn't
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* allow writing to an eeprom. It also doesn't provide any means of
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* accessing eeprom contents from within the kernel, only via sysfs.
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*/
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/* Added functionality for IBA7220-based cards */
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#define IPATH_EEPROM_DEV_V1 0xA0
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#define IPATH_EEPROM_DEV_V2 0xA2
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#define IPATH_TEMP_DEV 0x98
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#define IPATH_BAD_DEV (IPATH_EEPROM_DEV_V2+2)
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#define IPATH_NO_DEV (0xFF)
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/*
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* The number of I2C chains is proliferating. Table below brings
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* some order to the madness. The basic principle is that the
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* table is scanned from the top, and a "probe" is made to the
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* device probe_dev. If that succeeds, the chain is considered
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* to be of that type, and dd->i2c_chain_type is set to the index+1
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* of the entry.
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* The +1 is so static initialization can mean "unknown, do probe."
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*/
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static struct i2c_chain_desc {
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u8 probe_dev; /* If seen at probe, chain is this type */
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u8 eeprom_dev; /* Dev addr (if any) for EEPROM */
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u8 temp_dev; /* Dev Addr (if any) for Temp-sense */
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} i2c_chains[] = {
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{ IPATH_BAD_DEV, IPATH_NO_DEV, IPATH_NO_DEV }, /* pre-iba7220 bds */
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{ IPATH_EEPROM_DEV_V1, IPATH_EEPROM_DEV_V1, IPATH_TEMP_DEV}, /* V1 */
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{ IPATH_EEPROM_DEV_V2, IPATH_EEPROM_DEV_V2, IPATH_TEMP_DEV}, /* V2 */
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{ IPATH_NO_DEV }
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};
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enum i2c_type {
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i2c_line_scl = 0,
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i2c_line_sda
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};
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enum i2c_state {
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i2c_line_low = 0,
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i2c_line_high
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};
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#define READ_CMD 1
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#define WRITE_CMD 0
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/**
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* i2c_gpio_set - set a GPIO line
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* @dd: the infinipath device
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* @line: the line to set
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* @new_line_state: the state to set
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*
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* Returns 0 if the line was set to the new state successfully, non-zero
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* on error.
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*/
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static int i2c_gpio_set(struct ipath_devdata *dd,
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enum i2c_type line,
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enum i2c_state new_line_state)
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{
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u64 out_mask, dir_mask, *gpioval;
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unsigned long flags = 0;
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gpioval = &dd->ipath_gpio_out;
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if (line == i2c_line_scl) {
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dir_mask = dd->ipath_gpio_scl;
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out_mask = (1UL << dd->ipath_gpio_scl_num);
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} else {
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dir_mask = dd->ipath_gpio_sda;
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out_mask = (1UL << dd->ipath_gpio_sda_num);
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}
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spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
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if (new_line_state == i2c_line_high) {
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/* tri-state the output rather than force high */
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dd->ipath_extctrl &= ~dir_mask;
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} else {
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/* config line to be an output */
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dd->ipath_extctrl |= dir_mask;
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}
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ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, dd->ipath_extctrl);
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/* set output as well (no real verify) */
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if (new_line_state == i2c_line_high)
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*gpioval |= out_mask;
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else
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*gpioval &= ~out_mask;
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ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_out, *gpioval);
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spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
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return 0;
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}
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/**
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* i2c_gpio_get - get a GPIO line state
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* @dd: the infinipath device
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* @line: the line to get
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* @curr_statep: where to put the line state
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*
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* Returns 0 if the line was set to the new state successfully, non-zero
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* on error. curr_state is not set on error.
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*/
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static int i2c_gpio_get(struct ipath_devdata *dd,
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enum i2c_type line,
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enum i2c_state *curr_statep)
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{
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u64 read_val, mask;
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int ret;
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unsigned long flags = 0;
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/* check args */
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if (curr_statep == NULL) {
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ret = 1;
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goto bail;
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}
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/* config line to be an input */
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if (line == i2c_line_scl)
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mask = dd->ipath_gpio_scl;
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else
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mask = dd->ipath_gpio_sda;
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spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
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dd->ipath_extctrl &= ~mask;
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ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, dd->ipath_extctrl);
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/*
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* Below is very unlikely to reflect true input state if Output
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* Enable actually changed.
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*/
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read_val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
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spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
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if (read_val & mask)
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*curr_statep = i2c_line_high;
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else
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*curr_statep = i2c_line_low;
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ret = 0;
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bail:
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return ret;
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}
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/**
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* i2c_wait_for_writes - wait for a write
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* @dd: the infinipath device
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*
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* We use this instead of udelay directly, so we can make sure
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* that previous register writes have been flushed all the way
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* to the chip. Since we are delaying anyway, the cost doesn't
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* hurt, and makes the bit twiddling more regular
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*/
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static void i2c_wait_for_writes(struct ipath_devdata *dd)
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{
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(void)ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
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rmb();
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}
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static void scl_out(struct ipath_devdata *dd, u8 bit)
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{
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udelay(1);
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i2c_gpio_set(dd, i2c_line_scl, bit ? i2c_line_high : i2c_line_low);
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i2c_wait_for_writes(dd);
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}
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static void sda_out(struct ipath_devdata *dd, u8 bit)
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{
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i2c_gpio_set(dd, i2c_line_sda, bit ? i2c_line_high : i2c_line_low);
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i2c_wait_for_writes(dd);
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}
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static u8 sda_in(struct ipath_devdata *dd, int wait)
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{
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enum i2c_state bit;
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if (i2c_gpio_get(dd, i2c_line_sda, &bit))
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ipath_dbg("get bit failed!\n");
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if (wait)
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i2c_wait_for_writes(dd);
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return bit == i2c_line_high ? 1U : 0;
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}
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/**
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* i2c_ackrcv - see if ack following write is true
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* @dd: the infinipath device
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*/
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static int i2c_ackrcv(struct ipath_devdata *dd)
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{
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u8 ack_received;
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/* AT ENTRY SCL = LOW */
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/* change direction, ignore data */
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ack_received = sda_in(dd, 1);
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scl_out(dd, i2c_line_high);
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ack_received = sda_in(dd, 1) == 0;
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scl_out(dd, i2c_line_low);
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return ack_received;
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}
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/**
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* rd_byte - read a byte, leaving ACK, STOP, etc up to caller
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* @dd: the infinipath device
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*
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* Returns byte shifted out of device
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*/
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static int rd_byte(struct ipath_devdata *dd)
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{
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int bit_cntr, data;
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data = 0;
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for (bit_cntr = 7; bit_cntr >= 0; --bit_cntr) {
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data <<= 1;
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scl_out(dd, i2c_line_high);
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data |= sda_in(dd, 0);
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scl_out(dd, i2c_line_low);
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}
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return data;
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}
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/**
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* wr_byte - write a byte, one bit at a time
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* @dd: the infinipath device
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* @data: the byte to write
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*
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* Returns 0 if we got the following ack, otherwise 1
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*/
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static int wr_byte(struct ipath_devdata *dd, u8 data)
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{
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int bit_cntr;
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u8 bit;
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for (bit_cntr = 7; bit_cntr >= 0; bit_cntr--) {
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bit = (data >> bit_cntr) & 1;
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sda_out(dd, bit);
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scl_out(dd, i2c_line_high);
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scl_out(dd, i2c_line_low);
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}
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return (!i2c_ackrcv(dd)) ? 1 : 0;
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}
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static void send_ack(struct ipath_devdata *dd)
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{
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sda_out(dd, i2c_line_low);
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scl_out(dd, i2c_line_high);
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scl_out(dd, i2c_line_low);
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sda_out(dd, i2c_line_high);
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}
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/**
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* i2c_startcmd - transmit the start condition, followed by address/cmd
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* @dd: the infinipath device
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* @offset_dir: direction byte
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*
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* (both clock/data high, clock high, data low while clock is high)
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*/
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static int i2c_startcmd(struct ipath_devdata *dd, u8 offset_dir)
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{
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int res;
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/* issue start sequence */
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sda_out(dd, i2c_line_high);
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scl_out(dd, i2c_line_high);
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sda_out(dd, i2c_line_low);
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scl_out(dd, i2c_line_low);
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/* issue length and direction byte */
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res = wr_byte(dd, offset_dir);
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if (res)
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ipath_cdbg(VERBOSE, "No ack to complete start\n");
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return res;
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}
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/**
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* stop_cmd - transmit the stop condition
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* @dd: the infinipath device
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*
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* (both clock/data low, clock high, data high while clock is high)
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*/
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static void stop_cmd(struct ipath_devdata *dd)
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{
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scl_out(dd, i2c_line_low);
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sda_out(dd, i2c_line_low);
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scl_out(dd, i2c_line_high);
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sda_out(dd, i2c_line_high);
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udelay(2);
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}
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/**
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* eeprom_reset - reset I2C communication
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* @dd: the infinipath device
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*/
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static int eeprom_reset(struct ipath_devdata *dd)
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{
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int clock_cycles_left = 9;
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u64 *gpioval = &dd->ipath_gpio_out;
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int ret;
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unsigned long flags;
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spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
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/* Make sure shadows are consistent */
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dd->ipath_extctrl = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extctrl);
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*gpioval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_gpio_out);
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spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
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ipath_cdbg(VERBOSE, "Resetting i2c eeprom; initial gpioout reg "
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"is %llx\n", (unsigned long long) *gpioval);
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/*
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* This is to get the i2c into a known state, by first going low,
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* then tristate sda (and then tristate scl as first thing
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* in loop)
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*/
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scl_out(dd, i2c_line_low);
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sda_out(dd, i2c_line_high);
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/* Clock up to 9 cycles looking for SDA hi, then issue START and STOP */
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while (clock_cycles_left--) {
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scl_out(dd, i2c_line_high);
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|
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/* SDA seen high, issue START by dropping it while SCL high */
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if (sda_in(dd, 0)) {
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sda_out(dd, i2c_line_low);
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scl_out(dd, i2c_line_low);
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/* ATMEL spec says must be followed by STOP. */
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scl_out(dd, i2c_line_high);
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sda_out(dd, i2c_line_high);
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ret = 0;
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goto bail;
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}
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scl_out(dd, i2c_line_low);
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}
|
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|
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ret = 1;
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bail:
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return ret;
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}
|
|
|
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/*
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* Probe for I2C device at specified address. Returns 0 for "success"
|
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* to match rest of this file.
|
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* Leave bus in "reasonable" state for further commands.
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*/
|
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static int i2c_probe(struct ipath_devdata *dd, int devaddr)
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{
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int ret = 0;
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ret = eeprom_reset(dd);
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if (ret) {
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ipath_dev_err(dd, "Failed reset probing device 0x%02X\n",
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devaddr);
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return ret;
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}
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/*
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* Reset no longer leaves bus in start condition, so normal
|
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* i2c_startcmd() will do.
|
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*/
|
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ret = i2c_startcmd(dd, devaddr | READ_CMD);
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if (ret)
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ipath_cdbg(VERBOSE, "Failed startcmd for device 0x%02X\n",
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devaddr);
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else {
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/*
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* Device did respond. Complete a single-byte read, because some
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* devices apparently cannot handle STOP immediately after they
|
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* ACK the start-cmd.
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*/
|
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int data;
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data = rd_byte(dd);
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stop_cmd(dd);
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ipath_cdbg(VERBOSE, "Response from device 0x%02X\n", devaddr);
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}
|
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return ret;
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}
|
|
|
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/*
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* Returns the "i2c type". This is a pointer to a struct that describes
|
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* the I2C chain on this board. To minimize impact on struct ipath_devdata,
|
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* the (small integer) index into the table is actually memoized, rather
|
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* then the pointer.
|
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* Memoization is because the type is determined on the first call per chip.
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* An alternative would be to move type determination to early
|
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* init code.
|
|
*/
|
|
static struct i2c_chain_desc *ipath_i2c_type(struct ipath_devdata *dd)
|
|
{
|
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int idx;
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|
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/* Get memoized index, from previous successful probes */
|
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idx = dd->ipath_i2c_chain_type - 1;
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if (idx >= 0 && idx < (ARRAY_SIZE(i2c_chains) - 1))
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goto done;
|
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|
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idx = 0;
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while (i2c_chains[idx].probe_dev != IPATH_NO_DEV) {
|
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/* if probe succeeds, this is type */
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if (!i2c_probe(dd, i2c_chains[idx].probe_dev))
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break;
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++idx;
|
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}
|
|
|
|
/*
|
|
* Old EEPROM (first entry) may require a reset after probe,
|
|
* rather than being able to "start" after "stop"
|
|
*/
|
|
if (idx == 0)
|
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eeprom_reset(dd);
|
|
|
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if (i2c_chains[idx].probe_dev == IPATH_NO_DEV)
|
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idx = -1;
|
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else
|
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dd->ipath_i2c_chain_type = idx + 1;
|
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done:
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return (idx >= 0) ? i2c_chains + idx : NULL;
|
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}
|
|
|
|
static int ipath_eeprom_internal_read(struct ipath_devdata *dd,
|
|
u8 eeprom_offset, void *buffer, int len)
|
|
{
|
|
int ret;
|
|
struct i2c_chain_desc *icd;
|
|
u8 *bp = buffer;
|
|
|
|
ret = 1;
|
|
icd = ipath_i2c_type(dd);
|
|
if (!icd)
|
|
goto bail;
|
|
|
|
if (icd->eeprom_dev == IPATH_NO_DEV) {
|
|
/* legacy not-really-I2C */
|
|
ipath_cdbg(VERBOSE, "Start command only address\n");
|
|
eeprom_offset = (eeprom_offset << 1) | READ_CMD;
|
|
ret = i2c_startcmd(dd, eeprom_offset);
|
|
} else {
|
|
/* Actual I2C */
|
|
ipath_cdbg(VERBOSE, "Start command uses devaddr\n");
|
|
if (i2c_startcmd(dd, icd->eeprom_dev | WRITE_CMD)) {
|
|
ipath_dbg("Failed EEPROM startcmd\n");
|
|
stop_cmd(dd);
|
|
ret = 1;
|
|
goto bail;
|
|
}
|
|
ret = wr_byte(dd, eeprom_offset);
|
|
stop_cmd(dd);
|
|
if (ret) {
|
|
ipath_dev_err(dd, "Failed to write EEPROM address\n");
|
|
ret = 1;
|
|
goto bail;
|
|
}
|
|
ret = i2c_startcmd(dd, icd->eeprom_dev | READ_CMD);
|
|
}
|
|
if (ret) {
|
|
ipath_dbg("Failed startcmd for dev %02X\n", icd->eeprom_dev);
|
|
stop_cmd(dd);
|
|
ret = 1;
|
|
goto bail;
|
|
}
|
|
|
|
/*
|
|
* eeprom keeps clocking data out as long as we ack, automatically
|
|
* incrementing the address.
|
|
*/
|
|
while (len-- > 0) {
|
|
/* get and store data */
|
|
*bp++ = rd_byte(dd);
|
|
/* send ack if not the last byte */
|
|
if (len)
|
|
send_ack(dd);
|
|
}
|
|
|
|
stop_cmd(dd);
|
|
|
|
ret = 0;
|
|
|
|
bail:
|
|
return ret;
|
|
}
|
|
|
|
static int ipath_eeprom_internal_write(struct ipath_devdata *dd, u8 eeprom_offset,
|
|
const void *buffer, int len)
|
|
{
|
|
int sub_len;
|
|
const u8 *bp = buffer;
|
|
int max_wait_time, i;
|
|
int ret;
|
|
struct i2c_chain_desc *icd;
|
|
|
|
ret = 1;
|
|
icd = ipath_i2c_type(dd);
|
|
if (!icd)
|
|
goto bail;
|
|
|
|
while (len > 0) {
|
|
if (icd->eeprom_dev == IPATH_NO_DEV) {
|
|
if (i2c_startcmd(dd,
|
|
(eeprom_offset << 1) | WRITE_CMD)) {
|
|
ipath_dbg("Failed to start cmd offset %u\n",
|
|
eeprom_offset);
|
|
goto failed_write;
|
|
}
|
|
} else {
|
|
/* Real I2C */
|
|
if (i2c_startcmd(dd, icd->eeprom_dev | WRITE_CMD)) {
|
|
ipath_dbg("Failed EEPROM startcmd\n");
|
|
goto failed_write;
|
|
}
|
|
ret = wr_byte(dd, eeprom_offset);
|
|
if (ret) {
|
|
ipath_dev_err(dd, "Failed to write EEPROM "
|
|
"address\n");
|
|
goto failed_write;
|
|
}
|
|
}
|
|
|
|
sub_len = min(len, 4);
|
|
eeprom_offset += sub_len;
|
|
len -= sub_len;
|
|
|
|
for (i = 0; i < sub_len; i++) {
|
|
if (wr_byte(dd, *bp++)) {
|
|
ipath_dbg("no ack after byte %u/%u (%u "
|
|
"total remain)\n", i, sub_len,
|
|
len + sub_len - i);
|
|
goto failed_write;
|
|
}
|
|
}
|
|
|
|
stop_cmd(dd);
|
|
|
|
/*
|
|
* wait for write complete by waiting for a successful
|
|
* read (the chip replies with a zero after the write
|
|
* cmd completes, and before it writes to the eeprom.
|
|
* The startcmd for the read will fail the ack until
|
|
* the writes have completed. We do this inline to avoid
|
|
* the debug prints that are in the real read routine
|
|
* if the startcmd fails.
|
|
* We also use the proper device address, so it doesn't matter
|
|
* whether we have real eeprom_dev. legacy likes any address.
|
|
*/
|
|
max_wait_time = 100;
|
|
while (i2c_startcmd(dd, icd->eeprom_dev | READ_CMD)) {
|
|
stop_cmd(dd);
|
|
if (!--max_wait_time) {
|
|
ipath_dbg("Did not get successful read to "
|
|
"complete write\n");
|
|
goto failed_write;
|
|
}
|
|
}
|
|
/* now read (and ignore) the resulting byte */
|
|
rd_byte(dd);
|
|
stop_cmd(dd);
|
|
}
|
|
|
|
ret = 0;
|
|
goto bail;
|
|
|
|
failed_write:
|
|
stop_cmd(dd);
|
|
ret = 1;
|
|
|
|
bail:
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* ipath_eeprom_read - receives bytes from the eeprom via I2C
|
|
* @dd: the infinipath device
|
|
* @eeprom_offset: address to read from
|
|
* @buffer: where to store result
|
|
* @len: number of bytes to receive
|
|
*/
|
|
int ipath_eeprom_read(struct ipath_devdata *dd, u8 eeprom_offset,
|
|
void *buff, int len)
|
|
{
|
|
int ret;
|
|
|
|
ret = mutex_lock_interruptible(&dd->ipath_eep_lock);
|
|
if (!ret) {
|
|
ret = ipath_eeprom_internal_read(dd, eeprom_offset, buff, len);
|
|
mutex_unlock(&dd->ipath_eep_lock);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* ipath_eeprom_write - writes data to the eeprom via I2C
|
|
* @dd: the infinipath device
|
|
* @eeprom_offset: where to place data
|
|
* @buffer: data to write
|
|
* @len: number of bytes to write
|
|
*/
|
|
int ipath_eeprom_write(struct ipath_devdata *dd, u8 eeprom_offset,
|
|
const void *buff, int len)
|
|
{
|
|
int ret;
|
|
|
|
ret = mutex_lock_interruptible(&dd->ipath_eep_lock);
|
|
if (!ret) {
|
|
ret = ipath_eeprom_internal_write(dd, eeprom_offset, buff, len);
|
|
mutex_unlock(&dd->ipath_eep_lock);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static u8 flash_csum(struct ipath_flash *ifp, int adjust)
|
|
{
|
|
u8 *ip = (u8 *) ifp;
|
|
u8 csum = 0, len;
|
|
|
|
/*
|
|
* Limit length checksummed to max length of actual data.
|
|
* Checksum of erased eeprom will still be bad, but we avoid
|
|
* reading past the end of the buffer we were passed.
|
|
*/
|
|
len = ifp->if_length;
|
|
if (len > sizeof(struct ipath_flash))
|
|
len = sizeof(struct ipath_flash);
|
|
while (len--)
|
|
csum += *ip++;
|
|
csum -= ifp->if_csum;
|
|
csum = ~csum;
|
|
if (adjust)
|
|
ifp->if_csum = csum;
|
|
|
|
return csum;
|
|
}
|
|
|
|
/**
|
|
* ipath_get_guid - get the GUID from the i2c device
|
|
* @dd: the infinipath device
|
|
*
|
|
* We have the capability to use the ipath_nguid field, and get
|
|
* the guid from the first chip's flash, to use for all of them.
|
|
*/
|
|
void ipath_get_eeprom_info(struct ipath_devdata *dd)
|
|
{
|
|
void *buf;
|
|
struct ipath_flash *ifp;
|
|
__be64 guid;
|
|
int len, eep_stat;
|
|
u8 csum, *bguid;
|
|
int t = dd->ipath_unit;
|
|
struct ipath_devdata *dd0 = ipath_lookup(0);
|
|
|
|
if (t && dd0->ipath_nguid > 1 && t <= dd0->ipath_nguid) {
|
|
u8 oguid;
|
|
dd->ipath_guid = dd0->ipath_guid;
|
|
bguid = (u8 *) & dd->ipath_guid;
|
|
|
|
oguid = bguid[7];
|
|
bguid[7] += t;
|
|
if (oguid > bguid[7]) {
|
|
if (bguid[6] == 0xff) {
|
|
if (bguid[5] == 0xff) {
|
|
ipath_dev_err(
|
|
dd,
|
|
"Can't set %s GUID from "
|
|
"base, wraps to OUI!\n",
|
|
ipath_get_unit_name(t));
|
|
dd->ipath_guid = 0;
|
|
goto bail;
|
|
}
|
|
bguid[5]++;
|
|
}
|
|
bguid[6]++;
|
|
}
|
|
dd->ipath_nguid = 1;
|
|
|
|
ipath_dbg("nguid %u, so adding %u to device 0 guid, "
|
|
"for %llx\n",
|
|
dd0->ipath_nguid, t,
|
|
(unsigned long long) be64_to_cpu(dd->ipath_guid));
|
|
goto bail;
|
|
}
|
|
|
|
/*
|
|
* read full flash, not just currently used part, since it may have
|
|
* been written with a newer definition
|
|
* */
|
|
len = sizeof(struct ipath_flash);
|
|
buf = vmalloc(len);
|
|
if (!buf) {
|
|
ipath_dev_err(dd, "Couldn't allocate memory to read %u "
|
|
"bytes from eeprom for GUID\n", len);
|
|
goto bail;
|
|
}
|
|
|
|
mutex_lock(&dd->ipath_eep_lock);
|
|
eep_stat = ipath_eeprom_internal_read(dd, 0, buf, len);
|
|
mutex_unlock(&dd->ipath_eep_lock);
|
|
|
|
if (eep_stat) {
|
|
ipath_dev_err(dd, "Failed reading GUID from eeprom\n");
|
|
goto done;
|
|
}
|
|
ifp = (struct ipath_flash *)buf;
|
|
|
|
csum = flash_csum(ifp, 0);
|
|
if (csum != ifp->if_csum) {
|
|
dev_info(&dd->pcidev->dev, "Bad I2C flash checksum: "
|
|
"0x%x, not 0x%x\n", csum, ifp->if_csum);
|
|
goto done;
|
|
}
|
|
if (*(__be64 *) ifp->if_guid == 0ULL ||
|
|
*(__be64 *) ifp->if_guid == __constant_cpu_to_be64(-1LL)) {
|
|
ipath_dev_err(dd, "Invalid GUID %llx from flash; "
|
|
"ignoring\n",
|
|
*(unsigned long long *) ifp->if_guid);
|
|
/* don't allow GUID if all 0 or all 1's */
|
|
goto done;
|
|
}
|
|
|
|
/* complain, but allow it */
|
|
if (*(u64 *) ifp->if_guid == 0x100007511000000ULL)
|
|
dev_info(&dd->pcidev->dev, "Warning, GUID %llx is "
|
|
"default, probably not correct!\n",
|
|
*(unsigned long long *) ifp->if_guid);
|
|
|
|
bguid = ifp->if_guid;
|
|
if (!bguid[0] && !bguid[1] && !bguid[2]) {
|
|
/* original incorrect GUID format in flash; fix in
|
|
* core copy, by shifting up 2 octets; don't need to
|
|
* change top octet, since both it and shifted are
|
|
* 0.. */
|
|
bguid[1] = bguid[3];
|
|
bguid[2] = bguid[4];
|
|
bguid[3] = bguid[4] = 0;
|
|
guid = *(__be64 *) ifp->if_guid;
|
|
ipath_cdbg(VERBOSE, "Old GUID format in flash, top 3 zero, "
|
|
"shifting 2 octets\n");
|
|
} else
|
|
guid = *(__be64 *) ifp->if_guid;
|
|
dd->ipath_guid = guid;
|
|
dd->ipath_nguid = ifp->if_numguid;
|
|
/*
|
|
* Things are slightly complicated by the desire to transparently
|
|
* support both the Pathscale 10-digit serial number and the QLogic
|
|
* 13-character version.
|
|
*/
|
|
if ((ifp->if_fversion > 1) && ifp->if_sprefix[0]
|
|
&& ((u8 *)ifp->if_sprefix)[0] != 0xFF) {
|
|
/* This board has a Serial-prefix, which is stored
|
|
* elsewhere for backward-compatibility.
|
|
*/
|
|
char *snp = dd->ipath_serial;
|
|
memcpy(snp, ifp->if_sprefix, sizeof ifp->if_sprefix);
|
|
snp[sizeof ifp->if_sprefix] = '\0';
|
|
len = strlen(snp);
|
|
snp += len;
|
|
len = (sizeof dd->ipath_serial) - len;
|
|
if (len > sizeof ifp->if_serial) {
|
|
len = sizeof ifp->if_serial;
|
|
}
|
|
memcpy(snp, ifp->if_serial, len);
|
|
} else
|
|
memcpy(dd->ipath_serial, ifp->if_serial,
|
|
sizeof ifp->if_serial);
|
|
if (!strstr(ifp->if_comment, "Tested successfully"))
|
|
ipath_dev_err(dd, "Board SN %s did not pass functional "
|
|
"test: %s\n", dd->ipath_serial,
|
|
ifp->if_comment);
|
|
|
|
ipath_cdbg(VERBOSE, "Initted GUID to %llx from eeprom\n",
|
|
(unsigned long long) be64_to_cpu(dd->ipath_guid));
|
|
|
|
memcpy(&dd->ipath_eep_st_errs, &ifp->if_errcntp, IPATH_EEP_LOG_CNT);
|
|
/*
|
|
* Power-on (actually "active") hours are kept as little-endian value
|
|
* in EEPROM, but as seconds in a (possibly as small as 24-bit)
|
|
* atomic_t while running.
|
|
*/
|
|
atomic_set(&dd->ipath_active_time, 0);
|
|
dd->ipath_eep_hrs = ifp->if_powerhour[0] | (ifp->if_powerhour[1] << 8);
|
|
|
|
done:
|
|
vfree(buf);
|
|
|
|
bail:;
|
|
}
|
|
|
|
/**
|
|
* ipath_update_eeprom_log - copy active-time and error counters to eeprom
|
|
* @dd: the infinipath device
|
|
*
|
|
* Although the time is kept as seconds in the ipath_devdata struct, it is
|
|
* rounded to hours for re-write, as we have only 16 bits in EEPROM.
|
|
* First-cut code reads whole (expected) struct ipath_flash, modifies,
|
|
* re-writes. Future direction: read/write only what we need, assuming
|
|
* that the EEPROM had to have been "good enough" for driver init, and
|
|
* if not, we aren't making it worse.
|
|
*
|
|
*/
|
|
|
|
int ipath_update_eeprom_log(struct ipath_devdata *dd)
|
|
{
|
|
void *buf;
|
|
struct ipath_flash *ifp;
|
|
int len, hi_water;
|
|
uint32_t new_time, new_hrs;
|
|
u8 csum;
|
|
int ret, idx;
|
|
unsigned long flags;
|
|
|
|
/* first, check if we actually need to do anything. */
|
|
ret = 0;
|
|
for (idx = 0; idx < IPATH_EEP_LOG_CNT; ++idx) {
|
|
if (dd->ipath_eep_st_new_errs[idx]) {
|
|
ret = 1;
|
|
break;
|
|
}
|
|
}
|
|
new_time = atomic_read(&dd->ipath_active_time);
|
|
|
|
if (ret == 0 && new_time < 3600)
|
|
return 0;
|
|
|
|
/*
|
|
* The quick-check above determined that there is something worthy
|
|
* of logging, so get current contents and do a more detailed idea.
|
|
* read full flash, not just currently used part, since it may have
|
|
* been written with a newer definition
|
|
*/
|
|
len = sizeof(struct ipath_flash);
|
|
buf = vmalloc(len);
|
|
ret = 1;
|
|
if (!buf) {
|
|
ipath_dev_err(dd, "Couldn't allocate memory to read %u "
|
|
"bytes from eeprom for logging\n", len);
|
|
goto bail;
|
|
}
|
|
|
|
/* Grab semaphore and read current EEPROM. If we get an
|
|
* error, let go, but if not, keep it until we finish write.
|
|
*/
|
|
ret = mutex_lock_interruptible(&dd->ipath_eep_lock);
|
|
if (ret) {
|
|
ipath_dev_err(dd, "Unable to acquire EEPROM for logging\n");
|
|
goto free_bail;
|
|
}
|
|
ret = ipath_eeprom_internal_read(dd, 0, buf, len);
|
|
if (ret) {
|
|
mutex_unlock(&dd->ipath_eep_lock);
|
|
ipath_dev_err(dd, "Unable read EEPROM for logging\n");
|
|
goto free_bail;
|
|
}
|
|
ifp = (struct ipath_flash *)buf;
|
|
|
|
csum = flash_csum(ifp, 0);
|
|
if (csum != ifp->if_csum) {
|
|
mutex_unlock(&dd->ipath_eep_lock);
|
|
ipath_dev_err(dd, "EEPROM cks err (0x%02X, S/B 0x%02X)\n",
|
|
csum, ifp->if_csum);
|
|
ret = 1;
|
|
goto free_bail;
|
|
}
|
|
hi_water = 0;
|
|
spin_lock_irqsave(&dd->ipath_eep_st_lock, flags);
|
|
for (idx = 0; idx < IPATH_EEP_LOG_CNT; ++idx) {
|
|
int new_val = dd->ipath_eep_st_new_errs[idx];
|
|
if (new_val) {
|
|
/*
|
|
* If we have seen any errors, add to EEPROM values
|
|
* We need to saturate at 0xFF (255) and we also
|
|
* would need to adjust the checksum if we were
|
|
* trying to minimize EEPROM traffic
|
|
* Note that we add to actual current count in EEPROM,
|
|
* in case it was altered while we were running.
|
|
*/
|
|
new_val += ifp->if_errcntp[idx];
|
|
if (new_val > 0xFF)
|
|
new_val = 0xFF;
|
|
if (ifp->if_errcntp[idx] != new_val) {
|
|
ifp->if_errcntp[idx] = new_val;
|
|
hi_water = offsetof(struct ipath_flash,
|
|
if_errcntp) + idx;
|
|
}
|
|
/*
|
|
* update our shadow (used to minimize EEPROM
|
|
* traffic), to match what we are about to write.
|
|
*/
|
|
dd->ipath_eep_st_errs[idx] = new_val;
|
|
dd->ipath_eep_st_new_errs[idx] = 0;
|
|
}
|
|
}
|
|
/*
|
|
* now update active-time. We would like to round to the nearest hour
|
|
* but unless atomic_t are sure to be proper signed ints we cannot,
|
|
* because we need to account for what we "transfer" to EEPROM and
|
|
* if we log an hour at 31 minutes, then we would need to set
|
|
* active_time to -29 to accurately count the _next_ hour.
|
|
*/
|
|
if (new_time >= 3600) {
|
|
new_hrs = new_time / 3600;
|
|
atomic_sub((new_hrs * 3600), &dd->ipath_active_time);
|
|
new_hrs += dd->ipath_eep_hrs;
|
|
if (new_hrs > 0xFFFF)
|
|
new_hrs = 0xFFFF;
|
|
dd->ipath_eep_hrs = new_hrs;
|
|
if ((new_hrs & 0xFF) != ifp->if_powerhour[0]) {
|
|
ifp->if_powerhour[0] = new_hrs & 0xFF;
|
|
hi_water = offsetof(struct ipath_flash, if_powerhour);
|
|
}
|
|
if ((new_hrs >> 8) != ifp->if_powerhour[1]) {
|
|
ifp->if_powerhour[1] = new_hrs >> 8;
|
|
hi_water = offsetof(struct ipath_flash, if_powerhour)
|
|
+ 1;
|
|
}
|
|
}
|
|
/*
|
|
* There is a tiny possibility that we could somehow fail to write
|
|
* the EEPROM after updating our shadows, but problems from holding
|
|
* the spinlock too long are a much bigger issue.
|
|
*/
|
|
spin_unlock_irqrestore(&dd->ipath_eep_st_lock, flags);
|
|
if (hi_water) {
|
|
/* we made some change to the data, uopdate cksum and write */
|
|
csum = flash_csum(ifp, 1);
|
|
ret = ipath_eeprom_internal_write(dd, 0, buf, hi_water + 1);
|
|
}
|
|
mutex_unlock(&dd->ipath_eep_lock);
|
|
if (ret)
|
|
ipath_dev_err(dd, "Failed updating EEPROM\n");
|
|
|
|
free_bail:
|
|
vfree(buf);
|
|
bail:
|
|
return ret;
|
|
|
|
}
|
|
|
|
/**
|
|
* ipath_inc_eeprom_err - increment one of the four error counters
|
|
* that are logged to EEPROM.
|
|
* @dd: the infinipath device
|
|
* @eidx: 0..3, the counter to increment
|
|
* @incr: how much to add
|
|
*
|
|
* Each counter is 8-bits, and saturates at 255 (0xFF). They
|
|
* are copied to the EEPROM (aka flash) whenever ipath_update_eeprom_log()
|
|
* is called, but it can only be called in a context that allows sleep.
|
|
* This function can be called even at interrupt level.
|
|
*/
|
|
|
|
void ipath_inc_eeprom_err(struct ipath_devdata *dd, u32 eidx, u32 incr)
|
|
{
|
|
uint new_val;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&dd->ipath_eep_st_lock, flags);
|
|
new_val = dd->ipath_eep_st_new_errs[eidx] + incr;
|
|
if (new_val > 255)
|
|
new_val = 255;
|
|
dd->ipath_eep_st_new_errs[eidx] = new_val;
|
|
spin_unlock_irqrestore(&dd->ipath_eep_st_lock, flags);
|
|
return;
|
|
}
|
|
|
|
static int ipath_tempsense_internal_read(struct ipath_devdata *dd, u8 regnum)
|
|
{
|
|
int ret;
|
|
struct i2c_chain_desc *icd;
|
|
|
|
ret = -ENOENT;
|
|
|
|
icd = ipath_i2c_type(dd);
|
|
if (!icd)
|
|
goto bail;
|
|
|
|
if (icd->temp_dev == IPATH_NO_DEV) {
|
|
/* tempsense only exists on new, real-I2C boards */
|
|
ret = -ENXIO;
|
|
goto bail;
|
|
}
|
|
|
|
if (i2c_startcmd(dd, icd->temp_dev | WRITE_CMD)) {
|
|
ipath_dbg("Failed tempsense startcmd\n");
|
|
stop_cmd(dd);
|
|
ret = -ENXIO;
|
|
goto bail;
|
|
}
|
|
ret = wr_byte(dd, regnum);
|
|
stop_cmd(dd);
|
|
if (ret) {
|
|
ipath_dev_err(dd, "Failed tempsense WR command %02X\n",
|
|
regnum);
|
|
ret = -ENXIO;
|
|
goto bail;
|
|
}
|
|
if (i2c_startcmd(dd, icd->temp_dev | READ_CMD)) {
|
|
ipath_dbg("Failed tempsense RD startcmd\n");
|
|
stop_cmd(dd);
|
|
ret = -ENXIO;
|
|
goto bail;
|
|
}
|
|
/*
|
|
* We can only clock out one byte per command, sensibly
|
|
*/
|
|
ret = rd_byte(dd);
|
|
stop_cmd(dd);
|
|
|
|
bail:
|
|
return ret;
|
|
}
|
|
|
|
#define VALID_TS_RD_REG_MASK 0xBF
|
|
|
|
/**
|
|
* ipath_tempsense_read - read register of temp sensor via I2C
|
|
* @dd: the infinipath device
|
|
* @regnum: register to read from
|
|
*
|
|
* returns reg contents (0..255) or < 0 for error
|
|
*/
|
|
int ipath_tempsense_read(struct ipath_devdata *dd, u8 regnum)
|
|
{
|
|
int ret;
|
|
|
|
if (regnum > 7)
|
|
return -EINVAL;
|
|
|
|
/* return a bogus value for (the one) register we do not have */
|
|
if (!((1 << regnum) & VALID_TS_RD_REG_MASK))
|
|
return 0;
|
|
|
|
ret = mutex_lock_interruptible(&dd->ipath_eep_lock);
|
|
if (!ret) {
|
|
ret = ipath_tempsense_internal_read(dd, regnum);
|
|
mutex_unlock(&dd->ipath_eep_lock);
|
|
}
|
|
|
|
/*
|
|
* There are three possibilities here:
|
|
* ret is actual value (0..255)
|
|
* ret is -ENXIO or -EINVAL from code in this file
|
|
* ret is -EINTR from mutex_lock_interruptible.
|
|
*/
|
|
return ret;
|
|
}
|
|
|
|
static int ipath_tempsense_internal_write(struct ipath_devdata *dd,
|
|
u8 regnum, u8 data)
|
|
{
|
|
int ret = -ENOENT;
|
|
struct i2c_chain_desc *icd;
|
|
|
|
icd = ipath_i2c_type(dd);
|
|
if (!icd)
|
|
goto bail;
|
|
|
|
if (icd->temp_dev == IPATH_NO_DEV) {
|
|
/* tempsense only exists on new, real-I2C boards */
|
|
ret = -ENXIO;
|
|
goto bail;
|
|
}
|
|
if (i2c_startcmd(dd, icd->temp_dev | WRITE_CMD)) {
|
|
ipath_dbg("Failed tempsense startcmd\n");
|
|
stop_cmd(dd);
|
|
ret = -ENXIO;
|
|
goto bail;
|
|
}
|
|
ret = wr_byte(dd, regnum);
|
|
if (ret) {
|
|
stop_cmd(dd);
|
|
ipath_dev_err(dd, "Failed to write tempsense command %02X\n",
|
|
regnum);
|
|
ret = -ENXIO;
|
|
goto bail;
|
|
}
|
|
ret = wr_byte(dd, data);
|
|
stop_cmd(dd);
|
|
ret = i2c_startcmd(dd, icd->temp_dev | READ_CMD);
|
|
if (ret) {
|
|
ipath_dev_err(dd, "Failed tempsense data wrt to %02X\n",
|
|
regnum);
|
|
ret = -ENXIO;
|
|
}
|
|
|
|
bail:
|
|
return ret;
|
|
}
|
|
|
|
#define VALID_TS_WR_REG_MASK ((1 << 9) | (1 << 0xB) | (1 << 0xD))
|
|
|
|
/**
|
|
* ipath_tempsense_write - write register of temp sensor via I2C
|
|
* @dd: the infinipath device
|
|
* @regnum: register to write
|
|
* @data: data to write
|
|
*
|
|
* returns 0 for success or < 0 for error
|
|
*/
|
|
int ipath_tempsense_write(struct ipath_devdata *dd, u8 regnum, u8 data)
|
|
{
|
|
int ret;
|
|
|
|
if (regnum > 15 || !((1 << regnum) & VALID_TS_WR_REG_MASK))
|
|
return -EINVAL;
|
|
|
|
ret = mutex_lock_interruptible(&dd->ipath_eep_lock);
|
|
if (!ret) {
|
|
ret = ipath_tempsense_internal_write(dd, regnum, data);
|
|
mutex_unlock(&dd->ipath_eep_lock);
|
|
}
|
|
|
|
/*
|
|
* There are three possibilities here:
|
|
* ret is 0 for success
|
|
* ret is -ENXIO or -EINVAL from code in this file
|
|
* ret is -EINTR from mutex_lock_interruptible.
|
|
*/
|
|
return ret;
|
|
}
|