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a2a571b74a
When using CP15 cache operations (c7), we make sure that Rd (r0) is actually 0 as ARM 926 TRM is saying. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
108 lines
3.0 KiB
C
108 lines
3.0 KiB
C
#ifdef CONFIG_ARCH_AT91RM9200
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#include <mach/at91rm9200_mc.h>
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/*
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* The AT91RM9200 goes into self-refresh mode with this command, and will
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* terminate self-refresh automatically on the next SDRAM access.
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*
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* Self-refresh mode is exited as soon as a memory access is made, but we don't
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* know for sure when that happens. However, we need to restore the low-power
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* mode if it was enabled before going idle. Restoring low-power mode while
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* still in self-refresh is "not recommended", but seems to work.
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*/
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static inline u32 sdram_selfrefresh_enable(void)
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{
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u32 saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
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at91_sys_write(AT91_SDRAMC_LPR, 0);
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at91_sys_write(AT91_SDRAMC_SRR, 1);
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return saved_lpr;
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}
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#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
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#define wait_for_interrupt_enable() asm volatile ("mcr p15, 0, %0, c7, c0, 4" \
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: : "r" (0))
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#elif defined(CONFIG_ARCH_AT91CAP9)
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#include <mach/at91cap9_ddrsdr.h>
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static inline u32 sdram_selfrefresh_enable(void)
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{
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u32 saved_lpr, lpr;
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saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR);
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lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
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at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
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return saved_lpr;
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}
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#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr)
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#define wait_for_interrupt_enable() cpu_do_idle()
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#elif defined(CONFIG_ARCH_AT91SAM9G45)
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#include <mach/at91sam9_ddrsdr.h>
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/* We manage both DDRAM/SDRAM controllers, we need more than one value to
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* remember.
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*/
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static u32 saved_lpr1;
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static inline u32 sdram_selfrefresh_enable(void)
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{
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/* Those tow values allow us to delay self-refresh activation
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* to the maximum. */
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u32 lpr0, lpr1;
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u32 saved_lpr0;
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saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
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lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
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lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
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saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
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lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
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lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
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/* self-refresh mode now */
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at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
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at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
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return saved_lpr0;
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}
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#define sdram_selfrefresh_disable(saved_lpr0) \
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do { \
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at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \
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at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \
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} while (0)
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#define wait_for_interrupt_enable() cpu_do_idle()
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#else
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#include <mach/at91sam9_sdramc.h>
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#ifdef CONFIG_ARCH_AT91SAM9263
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/*
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* FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
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* handle those cases both here and in the Suspend-To-RAM support.
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*/
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#warning Assuming EB1 SDRAM controller is *NOT* used
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#endif
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static inline u32 sdram_selfrefresh_enable(void)
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{
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u32 saved_lpr, lpr;
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saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
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lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
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at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
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return saved_lpr;
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}
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#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr)
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#define wait_for_interrupt_enable() cpu_do_idle()
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#endif
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