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linux-next/drivers/fpga
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Linus Torvalds 96d4f267e4 Remove 'type' argument from access_ok() function 
Nobody has actually used the type (VERIFY_READ vs VERIFY_WRITE) argument
of the user address range verification function since we got rid of the
old racy i386-only code to walk page tables by hand.

It existed because the original 80386 would not honor the write protect
bit when in kernel mode, so you had to do COW by hand before doing any
user access.  But we haven't supported that in a long time, and these
days the 'type' argument is a purely historical artifact.

A discussion about extending 'user_access_begin()' to do the range
checking resulted this patch, because there is no way we're going to
move the old VERIFY_xyz interface to that model.  And it's best done at
the end of the merge window when I've done most of my merges, so let's
just get this done once and for all.

This patch was mostly done with a sed-script, with manual fix-ups for
the cases that weren't of the trivial 'access_ok(VERIFY_xyz' form.

There were a couple of notable cases:

 - csky still had the old "verify_area()" name as an alias.

 - the iter_iov code had magical hardcoded knowledge of the actual
   values of VERIFY_{READ,WRITE} (not that they mattered, since nothing
   really used it)

 - microblaze used the type argument for a debug printout

but other than those oddities this should be a total no-op patch.

I tried to fix up all architectures, did fairly extensive grepping for
access_ok() uses, and the changes are trivial, but I may have missed
something.  Any missed conversion should be trivially fixable, though.

Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2019-01-03 18:57:57 -08:00
..
altera-cvp.c fpga: altera-cvp: fix probing for multiple FPGAs on the bus 2018-11-26 20:12:05 +01:00
altera-fpga2sdram.c fpga: bridge: add devm_fpga_bridge_create 2018-10-16 11:13:50 +02:00
altera-freeze-bridge.c fpga: bridge: add devm_fpga_bridge_create 2018-10-16 11:13:50 +02:00
altera-hps2fpga.c fpga: bridge: add devm_fpga_bridge_create 2018-10-16 11:13:50 +02:00
altera-pr-ip-core-plat.c fpga: use SPDX 2018-05-25 18:23:56 +02:00
altera-pr-ip-core.c fpga: mgr: add devm_fpga_mgr_create 2018-10-16 11:13:50 +02:00
altera-ps-spi.c fpga: mgr: altera-ps-spi: enable usage on non-dt platforms 2018-11-26 20:12:05 +01:00
dfl-afu-dma-region.c Remove 'type' argument from access_ok() function 2019-01-03 18:57:57 -08:00
dfl-afu-main.c fpga: dfl: afu: add DFL_FPGA_PORT_DMA_MAP/UNMAP ioctls support 2018-07-15 13:55:47 +02:00
dfl-afu-region.c fpga: dfl: afu: add afu sub feature support 2018-07-15 13:55:47 +02:00
dfl-afu.h fpga: dfl: afu: add DFL_FPGA_PORT_DMA_MAP/UNMAP ioctls support 2018-07-15 13:55:47 +02:00
dfl-fme-br.c fpga: bridge: add devm_fpga_bridge_create 2018-10-16 11:13:50 +02:00
dfl-fme-main.c fpga: dfl: fme: add partial reconfiguration sub feature support 2018-07-15 13:55:46 +02:00
dfl-fme-mgr.c fpga: mgr: add devm_fpga_mgr_create 2018-10-16 11:13:50 +02:00
dfl-fme-pr.c Remove 'type' argument from access_ok() function 2019-01-03 18:57:57 -08:00
dfl-fme-pr.h fpga: dfl: fme: add partial reconfiguration sub feature support 2018-07-15 13:55:46 +02:00
dfl-fme-region.c fpga: dfl-fme-region: Use platform_get_drvdata() 2018-11-26 20:47:10 +01:00
dfl-fme.h fpga: dfl: fme: add partial reconfiguration sub feature support 2018-07-15 13:55:46 +02:00
dfl-pci.c fpga: dfl-pci: add enumeration for feature devices 2018-07-15 13:55:45 +02:00
dfl.c fpga: add devm_fpga_region_create 2018-10-16 11:13:50 +02:00
dfl.h fpga: dfl: add dfl_fpga_check_port_id function. 2018-07-15 13:55:45 +02:00
fpga-bridge.c fpga: bridge: add devm_fpga_bridge_create 2018-10-16 11:13:50 +02:00
fpga-mgr.c fpga: mgr: add devm_fpga_mgr_create 2018-10-16 11:13:50 +02:00
fpga-region.c fpga: add devm_fpga_region_create 2018-10-16 11:13:50 +02:00
ice40-spi.c fpga: mgr: add devm_fpga_mgr_create 2018-10-16 11:13:50 +02:00
Kconfig fpga: add intel stratix10 soc fpga manager driver 2018-11-26 20:15:07 +01:00
machxo2-spi.c fpga: mgr: add devm_fpga_mgr_create 2018-10-16 11:13:50 +02:00
Makefile fpga: add intel stratix10 soc fpga manager driver 2018-11-26 20:15:07 +01:00
of-fpga-region.c fpga: of-fpga-region: Use platform_set_drvdata 2018-11-26 20:47:10 +01:00
socfpga-a10.c fpga: mgr: add devm_fpga_mgr_create 2018-10-16 11:13:50 +02:00
socfpga.c fpga: mgr: add devm_fpga_mgr_create 2018-10-16 11:13:50 +02:00
stratix10-soc.c fpga: add intel stratix10 soc fpga manager driver 2018-11-26 20:15:07 +01:00
ts73xx-fpga.c fpga: mgr: add devm_fpga_mgr_create 2018-10-16 11:13:50 +02:00
xilinx-pr-decoupler.c fpga: bridge: add devm_fpga_bridge_create 2018-10-16 11:13:50 +02:00
xilinx-spi.c fpga: mgr: add devm_fpga_mgr_create 2018-10-16 11:13:50 +02:00
zynq-fpga.c zynq-fpga: Only route PR via PCAP when required 2018-11-11 12:58:27 -08:00