mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-23 04:34:11 +08:00
bd0b9ac405
Most interrupt flow handlers do not use the irq argument. Those few which use it can retrieve the irq number from the irq descriptor. Remove the argument. Search and replace was done with coccinelle and some extra helper scripts around it. Thanks to Julia for her help! Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com>
537 lines
12 KiB
C
537 lines
12 KiB
C
/*
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* Driver for Motorola PCAP2 as present in EZX phones
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*
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* Copyright (C) 2006 Harald Welte <laforge@openezx.org>
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* Copyright (C) 2009 Daniel Ribeiro <drwyrm@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/mfd/ezx-pcap.h>
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#include <linux/spi/spi.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#define PCAP_ADC_MAXQ 8
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struct pcap_adc_request {
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u8 bank;
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u8 ch[2];
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u32 flags;
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void (*callback)(void *, u16[]);
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void *data;
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};
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struct pcap_adc_sync_request {
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u16 res[2];
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struct completion completion;
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};
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struct pcap_chip {
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struct spi_device *spi;
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/* IO */
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u32 buf;
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struct mutex io_mutex;
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/* IRQ */
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unsigned int irq_base;
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u32 msr;
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struct work_struct isr_work;
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struct work_struct msr_work;
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struct workqueue_struct *workqueue;
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/* ADC */
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struct pcap_adc_request *adc_queue[PCAP_ADC_MAXQ];
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u8 adc_head;
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u8 adc_tail;
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struct mutex adc_mutex;
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};
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/* IO */
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static int ezx_pcap_putget(struct pcap_chip *pcap, u32 *data)
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{
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struct spi_transfer t;
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struct spi_message m;
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int status;
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memset(&t, 0, sizeof(t));
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spi_message_init(&m);
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t.len = sizeof(u32);
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spi_message_add_tail(&t, &m);
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pcap->buf = *data;
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t.tx_buf = (u8 *) &pcap->buf;
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t.rx_buf = (u8 *) &pcap->buf;
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status = spi_sync(pcap->spi, &m);
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if (status == 0)
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*data = pcap->buf;
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return status;
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}
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int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value)
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{
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int ret;
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mutex_lock(&pcap->io_mutex);
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value &= PCAP_REGISTER_VALUE_MASK;
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value |= PCAP_REGISTER_WRITE_OP_BIT
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| (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
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ret = ezx_pcap_putget(pcap, &value);
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mutex_unlock(&pcap->io_mutex);
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return ret;
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}
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EXPORT_SYMBOL_GPL(ezx_pcap_write);
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int ezx_pcap_read(struct pcap_chip *pcap, u8 reg_num, u32 *value)
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{
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int ret;
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mutex_lock(&pcap->io_mutex);
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*value = PCAP_REGISTER_READ_OP_BIT
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| (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
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ret = ezx_pcap_putget(pcap, value);
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mutex_unlock(&pcap->io_mutex);
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return ret;
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}
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EXPORT_SYMBOL_GPL(ezx_pcap_read);
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int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val)
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{
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int ret;
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u32 tmp = PCAP_REGISTER_READ_OP_BIT |
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(reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
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mutex_lock(&pcap->io_mutex);
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ret = ezx_pcap_putget(pcap, &tmp);
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if (ret)
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goto out_unlock;
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tmp &= (PCAP_REGISTER_VALUE_MASK & ~mask);
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tmp |= (val & mask) | PCAP_REGISTER_WRITE_OP_BIT |
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(reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
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ret = ezx_pcap_putget(pcap, &tmp);
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out_unlock:
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mutex_unlock(&pcap->io_mutex);
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return ret;
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}
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EXPORT_SYMBOL_GPL(ezx_pcap_set_bits);
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/* IRQ */
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int irq_to_pcap(struct pcap_chip *pcap, int irq)
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{
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return irq - pcap->irq_base;
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}
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EXPORT_SYMBOL_GPL(irq_to_pcap);
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int pcap_to_irq(struct pcap_chip *pcap, int irq)
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{
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return pcap->irq_base + irq;
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}
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EXPORT_SYMBOL_GPL(pcap_to_irq);
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static void pcap_mask_irq(struct irq_data *d)
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{
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struct pcap_chip *pcap = irq_data_get_irq_chip_data(d);
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pcap->msr |= 1 << irq_to_pcap(pcap, d->irq);
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queue_work(pcap->workqueue, &pcap->msr_work);
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}
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static void pcap_unmask_irq(struct irq_data *d)
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{
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struct pcap_chip *pcap = irq_data_get_irq_chip_data(d);
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pcap->msr &= ~(1 << irq_to_pcap(pcap, d->irq));
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queue_work(pcap->workqueue, &pcap->msr_work);
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}
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static struct irq_chip pcap_irq_chip = {
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.name = "pcap",
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.irq_disable = pcap_mask_irq,
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.irq_mask = pcap_mask_irq,
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.irq_unmask = pcap_unmask_irq,
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};
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static void pcap_msr_work(struct work_struct *work)
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{
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struct pcap_chip *pcap = container_of(work, struct pcap_chip, msr_work);
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ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
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}
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static void pcap_isr_work(struct work_struct *work)
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{
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struct pcap_chip *pcap = container_of(work, struct pcap_chip, isr_work);
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struct pcap_platform_data *pdata = dev_get_platdata(&pcap->spi->dev);
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u32 msr, isr, int_sel, service;
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int irq;
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do {
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ezx_pcap_read(pcap, PCAP_REG_MSR, &msr);
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ezx_pcap_read(pcap, PCAP_REG_ISR, &isr);
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/* We can't service/ack irqs that are assigned to port 2 */
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if (!(pdata->config & PCAP_SECOND_PORT)) {
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ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel);
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isr &= ~int_sel;
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}
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ezx_pcap_write(pcap, PCAP_REG_MSR, isr | msr);
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ezx_pcap_write(pcap, PCAP_REG_ISR, isr);
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local_irq_disable();
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service = isr & ~msr;
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for (irq = pcap->irq_base; service; service >>= 1, irq++) {
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if (service & 1)
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generic_handle_irq(irq);
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}
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local_irq_enable();
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ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
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} while (gpio_get_value(pdata->gpio));
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}
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static void pcap_irq_handler(struct irq_desc *desc)
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{
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struct pcap_chip *pcap = irq_desc_get_handler_data(desc);
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desc->irq_data.chip->irq_ack(&desc->irq_data);
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queue_work(pcap->workqueue, &pcap->isr_work);
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}
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/* ADC */
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void pcap_set_ts_bits(struct pcap_chip *pcap, u32 bits)
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{
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u32 tmp;
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mutex_lock(&pcap->adc_mutex);
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ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
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tmp &= ~(PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
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tmp |= bits & (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
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ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
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mutex_unlock(&pcap->adc_mutex);
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}
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EXPORT_SYMBOL_GPL(pcap_set_ts_bits);
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static void pcap_disable_adc(struct pcap_chip *pcap)
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{
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u32 tmp;
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ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
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tmp &= ~(PCAP_ADC_ADEN|PCAP_ADC_BATT_I_ADC|PCAP_ADC_BATT_I_POLARITY);
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ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
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}
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static void pcap_adc_trigger(struct pcap_chip *pcap)
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{
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u32 tmp;
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u8 head;
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mutex_lock(&pcap->adc_mutex);
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head = pcap->adc_head;
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if (!pcap->adc_queue[head]) {
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/* queue is empty, save power */
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pcap_disable_adc(pcap);
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mutex_unlock(&pcap->adc_mutex);
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return;
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}
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/* start conversion on requested bank, save TS_M bits */
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ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
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tmp &= (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
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tmp |= pcap->adc_queue[head]->flags | PCAP_ADC_ADEN;
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if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1)
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tmp |= PCAP_ADC_AD_SEL1;
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ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
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mutex_unlock(&pcap->adc_mutex);
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ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC);
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}
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static irqreturn_t pcap_adc_irq(int irq, void *_pcap)
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{
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struct pcap_chip *pcap = _pcap;
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struct pcap_adc_request *req;
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u16 res[2];
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u32 tmp;
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mutex_lock(&pcap->adc_mutex);
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req = pcap->adc_queue[pcap->adc_head];
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if (WARN(!req, "adc irq without pending request\n")) {
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mutex_unlock(&pcap->adc_mutex);
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return IRQ_HANDLED;
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}
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/* read requested channels results */
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ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
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tmp &= ~(PCAP_ADC_ADA1_MASK | PCAP_ADC_ADA2_MASK);
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tmp |= (req->ch[0] << PCAP_ADC_ADA1_SHIFT);
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tmp |= (req->ch[1] << PCAP_ADC_ADA2_SHIFT);
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ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
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ezx_pcap_read(pcap, PCAP_REG_ADR, &tmp);
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res[0] = (tmp & PCAP_ADR_ADD1_MASK) >> PCAP_ADR_ADD1_SHIFT;
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res[1] = (tmp & PCAP_ADR_ADD2_MASK) >> PCAP_ADR_ADD2_SHIFT;
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pcap->adc_queue[pcap->adc_head] = NULL;
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pcap->adc_head = (pcap->adc_head + 1) & (PCAP_ADC_MAXQ - 1);
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mutex_unlock(&pcap->adc_mutex);
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/* pass the results and release memory */
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req->callback(req->data, res);
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kfree(req);
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/* trigger next conversion (if any) on queue */
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pcap_adc_trigger(pcap);
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return IRQ_HANDLED;
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}
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int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
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void *callback, void *data)
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{
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struct pcap_adc_request *req;
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/* This will be freed after we have a result */
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req = kmalloc(sizeof(struct pcap_adc_request), GFP_KERNEL);
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if (!req)
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return -ENOMEM;
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req->bank = bank;
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req->flags = flags;
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req->ch[0] = ch[0];
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req->ch[1] = ch[1];
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req->callback = callback;
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req->data = data;
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mutex_lock(&pcap->adc_mutex);
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if (pcap->adc_queue[pcap->adc_tail]) {
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mutex_unlock(&pcap->adc_mutex);
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kfree(req);
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return -EBUSY;
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}
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pcap->adc_queue[pcap->adc_tail] = req;
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pcap->adc_tail = (pcap->adc_tail + 1) & (PCAP_ADC_MAXQ - 1);
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mutex_unlock(&pcap->adc_mutex);
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/* start conversion */
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pcap_adc_trigger(pcap);
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return 0;
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}
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EXPORT_SYMBOL_GPL(pcap_adc_async);
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static void pcap_adc_sync_cb(void *param, u16 res[])
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{
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struct pcap_adc_sync_request *req = param;
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req->res[0] = res[0];
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req->res[1] = res[1];
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complete(&req->completion);
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}
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int pcap_adc_sync(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
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u16 res[])
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{
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struct pcap_adc_sync_request sync_data;
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int ret;
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init_completion(&sync_data.completion);
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ret = pcap_adc_async(pcap, bank, flags, ch, pcap_adc_sync_cb,
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&sync_data);
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if (ret)
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return ret;
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wait_for_completion(&sync_data.completion);
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res[0] = sync_data.res[0];
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res[1] = sync_data.res[1];
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return 0;
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}
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EXPORT_SYMBOL_GPL(pcap_adc_sync);
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/* subdevs */
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static int pcap_remove_subdev(struct device *dev, void *unused)
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{
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platform_device_unregister(to_platform_device(dev));
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return 0;
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}
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static int pcap_add_subdev(struct pcap_chip *pcap,
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struct pcap_subdev *subdev)
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{
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struct platform_device *pdev;
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int ret;
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pdev = platform_device_alloc(subdev->name, subdev->id);
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if (!pdev)
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return -ENOMEM;
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pdev->dev.parent = &pcap->spi->dev;
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pdev->dev.platform_data = subdev->platform_data;
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ret = platform_device_add(pdev);
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if (ret)
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platform_device_put(pdev);
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return ret;
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}
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static int ezx_pcap_remove(struct spi_device *spi)
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{
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struct pcap_chip *pcap = spi_get_drvdata(spi);
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int i;
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/* remove all registered subdevs */
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device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
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/* cleanup ADC */
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mutex_lock(&pcap->adc_mutex);
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for (i = 0; i < PCAP_ADC_MAXQ; i++)
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kfree(pcap->adc_queue[i]);
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mutex_unlock(&pcap->adc_mutex);
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/* cleanup irqchip */
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for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
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irq_set_chip_and_handler(i, NULL, NULL);
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destroy_workqueue(pcap->workqueue);
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return 0;
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}
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static int ezx_pcap_probe(struct spi_device *spi)
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{
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struct pcap_platform_data *pdata = dev_get_platdata(&spi->dev);
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struct pcap_chip *pcap;
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int i, adc_irq;
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int ret = -ENODEV;
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/* platform data is required */
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if (!pdata)
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goto ret;
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pcap = devm_kzalloc(&spi->dev, sizeof(*pcap), GFP_KERNEL);
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if (!pcap) {
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ret = -ENOMEM;
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goto ret;
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}
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mutex_init(&pcap->io_mutex);
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mutex_init(&pcap->adc_mutex);
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INIT_WORK(&pcap->isr_work, pcap_isr_work);
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INIT_WORK(&pcap->msr_work, pcap_msr_work);
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spi_set_drvdata(spi, pcap);
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/* setup spi */
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spi->bits_per_word = 32;
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spi->mode = SPI_MODE_0 | (pdata->config & PCAP_CS_AH ? SPI_CS_HIGH : 0);
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ret = spi_setup(spi);
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if (ret)
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goto ret;
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pcap->spi = spi;
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/* setup irq */
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pcap->irq_base = pdata->irq_base;
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pcap->workqueue = create_singlethread_workqueue("pcapd");
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if (!pcap->workqueue) {
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ret = -ENOMEM;
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dev_err(&spi->dev, "can't create pcap thread\n");
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goto ret;
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}
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/* redirect interrupts to AP, except adcdone2 */
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if (!(pdata->config & PCAP_SECOND_PORT))
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ezx_pcap_write(pcap, PCAP_REG_INT_SEL,
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(1 << PCAP_IRQ_ADCDONE2));
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/* setup irq chip */
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for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) {
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irq_set_chip_and_handler(i, &pcap_irq_chip, handle_simple_irq);
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irq_set_chip_data(i, pcap);
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irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
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}
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/* mask/ack all PCAP interrupts */
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ezx_pcap_write(pcap, PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT);
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ezx_pcap_write(pcap, PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER);
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pcap->msr = PCAP_MASK_ALL_INTERRUPT;
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irq_set_irq_type(spi->irq, IRQ_TYPE_EDGE_RISING);
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irq_set_chained_handler_and_data(spi->irq, pcap_irq_handler, pcap);
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irq_set_irq_wake(spi->irq, 1);
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/* ADC */
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adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?
|
|
PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);
|
|
|
|
ret = devm_request_irq(&spi->dev, adc_irq, pcap_adc_irq, 0, "ADC",
|
|
pcap);
|
|
if (ret)
|
|
goto free_irqchip;
|
|
|
|
/* setup subdevs */
|
|
for (i = 0; i < pdata->num_subdevs; i++) {
|
|
ret = pcap_add_subdev(pcap, &pdata->subdevs[i]);
|
|
if (ret)
|
|
goto remove_subdevs;
|
|
}
|
|
|
|
/* board specific quirks */
|
|
if (pdata->init)
|
|
pdata->init(pcap);
|
|
|
|
return 0;
|
|
|
|
remove_subdevs:
|
|
device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
|
|
free_irqchip:
|
|
for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
|
|
irq_set_chip_and_handler(i, NULL, NULL);
|
|
/* destroy_workqueue: */
|
|
destroy_workqueue(pcap->workqueue);
|
|
ret:
|
|
return ret;
|
|
}
|
|
|
|
static struct spi_driver ezxpcap_driver = {
|
|
.probe = ezx_pcap_probe,
|
|
.remove = ezx_pcap_remove,
|
|
.driver = {
|
|
.name = "ezx-pcap",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static int __init ezx_pcap_init(void)
|
|
{
|
|
return spi_register_driver(&ezxpcap_driver);
|
|
}
|
|
|
|
static void __exit ezx_pcap_exit(void)
|
|
{
|
|
spi_unregister_driver(&ezxpcap_driver);
|
|
}
|
|
|
|
subsys_initcall(ezx_pcap_init);
|
|
module_exit(ezx_pcap_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Daniel Ribeiro / Harald Welte");
|
|
MODULE_DESCRIPTION("Motorola PCAP2 ASIC Driver");
|
|
MODULE_ALIAS("spi:ezx-pcap");
|