mirror of
https://github.com/edk2-porting/linux-next.git
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e761f6f332
Now that highbank uses the write_sec method, we don't need to enable the L2 cache in SoC specific code; this can be done via the normal mechanisms in the L2C code. Checking with Rob Herring: > > Can we kill the "highbank_smc1(0x102, 0x1);" here? That means > > l2x0_of_init() will see the L2 cache disabled, and will try to enable > > it via the write_sec hook, so it should do the right thing. > > Yes, that should work. You should be able to just call l2x0_of_init > unconditionally. The condition was really to just avoid the smc on > Midway which does get handled on h/w, but not if running virtualized. So also drop the DT check too. I'm leaving the config check in place so that if L2 is disabled, the write_sec hook can be optimised away. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
193 lines
4.6 KiB
C
193 lines
4.6 KiB
C
/*
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* Copyright 2010-2011 Calxeda, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clocksource.h>
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#include <linux/dma-mapping.h>
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#include <linux/input.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/mailbox.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/reboot.h>
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#include <linux/amba/bus.h>
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#include <linux/platform_device.h>
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#include <asm/psci.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include "core.h"
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#include "sysregs.h"
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void __iomem *sregs_base;
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void __iomem *scu_base_addr;
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static void __init highbank_scu_map_io(void)
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{
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unsigned long base;
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/* Get SCU base */
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asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
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scu_base_addr = ioremap(base, SZ_4K);
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}
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static void highbank_l2c310_write_sec(unsigned long val, unsigned reg)
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{
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if (reg == L2X0_CTRL)
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highbank_smc1(0x102, val);
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else
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WARN_ONCE(1, "Highbank L2C310: ignoring write to reg 0x%x\n",
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reg);
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}
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static void __init highbank_init_irq(void)
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{
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irqchip_init();
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if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
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highbank_scu_map_io();
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/* Enable PL310 L2 Cache controller */
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if (IS_ENABLED(CONFIG_CACHE_L2X0)) {
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outer_cache.write_sec = highbank_l2c310_write_sec;
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l2x0_of_init(0, ~0);
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}
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}
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static void highbank_power_off(void)
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{
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highbank_set_pwr_shutdown();
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while (1)
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cpu_do_idle();
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}
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static int highbank_platform_notifier(struct notifier_block *nb,
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unsigned long event, void *__dev)
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{
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struct resource *res;
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int reg = -1;
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u32 val;
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struct device *dev = __dev;
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if (event != BUS_NOTIFY_ADD_DEVICE)
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return NOTIFY_DONE;
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if (of_device_is_compatible(dev->of_node, "calxeda,hb-ahci"))
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reg = 0xc;
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else if (of_device_is_compatible(dev->of_node, "calxeda,hb-sdhci"))
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reg = 0x18;
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else if (of_device_is_compatible(dev->of_node, "arm,pl330"))
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reg = 0x20;
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else if (of_device_is_compatible(dev->of_node, "calxeda,hb-xgmac")) {
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res = platform_get_resource(to_platform_device(dev),
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IORESOURCE_MEM, 0);
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if (res) {
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if (res->start == 0xfff50000)
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reg = 0;
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else if (res->start == 0xfff51000)
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reg = 4;
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}
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}
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if (reg < 0)
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return NOTIFY_DONE;
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if (of_property_read_bool(dev->of_node, "dma-coherent")) {
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val = readl(sregs_base + reg);
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writel(val | 0xff01, sregs_base + reg);
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set_dma_ops(dev, &arm_coherent_dma_ops);
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}
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return NOTIFY_OK;
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}
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static struct notifier_block highbank_amba_nb = {
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.notifier_call = highbank_platform_notifier,
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};
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static struct notifier_block highbank_platform_nb = {
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.notifier_call = highbank_platform_notifier,
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};
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static struct platform_device highbank_cpuidle_device = {
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.name = "cpuidle-calxeda",
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};
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static int hb_keys_notifier(struct notifier_block *nb, unsigned long event, void *data)
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{
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u32 key = *(u32 *)data;
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if (event != 0x1000)
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return 0;
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if (key == KEY_POWER)
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orderly_poweroff(false);
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else if (key == 0xffff)
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ctrl_alt_del();
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return 0;
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}
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static struct notifier_block hb_keys_nb = {
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.notifier_call = hb_keys_notifier,
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};
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static void __init highbank_init(void)
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{
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struct device_node *np;
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/* Map system registers */
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np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
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sregs_base = of_iomap(np, 0);
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WARN_ON(!sregs_base);
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pm_power_off = highbank_power_off;
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highbank_pm_init();
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bus_register_notifier(&platform_bus_type, &highbank_platform_nb);
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bus_register_notifier(&amba_bustype, &highbank_amba_nb);
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pl320_ipc_register_notifier(&hb_keys_nb);
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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if (psci_ops.cpu_suspend)
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platform_device_register(&highbank_cpuidle_device);
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}
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static const char *highbank_match[] __initconst = {
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"calxeda,highbank",
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"calxeda,ecx-2000",
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NULL,
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};
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DT_MACHINE_START(HIGHBANK, "Highbank")
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#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)
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.dma_zone_size = (4ULL * SZ_1G),
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#endif
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.init_irq = highbank_init_irq,
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.init_machine = highbank_init,
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.dt_compat = highbank_match,
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.restart = highbank_restart,
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MACHINE_END
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