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7ab365f6cd
Maintain bitmaps of wake-enabled IRQs and mux inputs, and program them
to the hardware during the syscore phase of suspend and shutdown. Then
restore the original set of enabled IRQs (only the NMI) during resume.
This serves two purposes. First, it lets power management firmware
running on the ARISC coprocessor know which wakeup sources Linux wants
to have enabled. That way, it can avoid turning them off when it shuts
down the remainder of the clock tree. Second, it preconfigures the
coprocessor's interrupt controller, so the firmware's wakeup logic
is as simple as waiting for an interrupt to arrive.
The suspend/resume logic is not conditional on PM_SLEEP because it is
identical to the init/shutdown logic. Wake IRQs may be enabled during
shutdown to allow powering the board back on. As an example, see
commit a5c5e50cce
("Input: gpio-keys - add shutdown callback").
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210118055040.21910-5-samuel@sholland.org
380 lines
12 KiB
C
380 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* The R_INTC in Allwinner A31 and newer SoCs manages several types of
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* interrupts, as shown below:
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*
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* NMI IRQ DIRECT IRQs MUXED IRQs
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* bit 0 bits 1-15^ bits 19-31
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*
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* +---------+ +---------+ +---------+ +---------+
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* | NMI Pad | | IRQ d | | IRQ m | | IRQ m+7 |
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* +---------+ +---------+ +---------+ +---------+
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* | | | | | | |
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* | | | | |......| |
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* +------V------+ +------------+ | | | +--V------V--+ |
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* | Invert/ | | Write 1 to | | | | | AND with | |
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* | Edge Detect | | PENDING[0] | | | | | MUX[m/8] | |
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* +-------------+ +------------+ | | | +------------+ |
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* | | | | | | |
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* +--V-------V--+ +--V--+ | +--V--+ | +--V--+
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* | Set Reset| | GIC | | | GIC | | | GIC |
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* | Latch | | SPI | | | SPI |... | ...| SPI |
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* +-------------+ | N+d | | | m | | | m+7 |
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* | | +-----+ | +-----+ | +-----+
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* | | | |
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* +-------V-+ +-V----------+ +---------V--+ +--------V--------+
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* | GIC SPI | | AND with | | AND with | | AND with |
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* | N (=32) | | ENABLE[0] | | ENABLE[d] | | ENABLE[19+m/8] |
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* +---------+ +------------+ +------------+ +-----------------+
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* | | |
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* +------V-----+ +------V-----+ +--------V--------+
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* | Read | | Read | | Read |
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* | PENDING[0] | | PENDING[d] | | PENDING[19+m/8] |
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* +------------+ +------------+ +-----------------+
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*
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* ^ bits 16-18 are direct IRQs for peripherals with banked interrupts, such as
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* the MSGBOX. These IRQs do not map to any GIC SPI.
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*
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* The H6 variant adds two more (banked) direct IRQs and implements the full
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* set of 128 mux bits. This requires a second set of top-level registers.
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*/
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#include <linux/bitmap.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/syscore_ops.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#define SUN6I_NMI_CTRL (0x0c)
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#define SUN6I_IRQ_PENDING(n) (0x10 + 4 * (n))
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#define SUN6I_IRQ_ENABLE(n) (0x40 + 4 * (n))
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#define SUN6I_MUX_ENABLE(n) (0xc0 + 4 * (n))
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#define SUN6I_NMI_SRC_TYPE_LEVEL_LOW 0
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#define SUN6I_NMI_SRC_TYPE_EDGE_FALLING 1
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#define SUN6I_NMI_SRC_TYPE_LEVEL_HIGH 2
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#define SUN6I_NMI_SRC_TYPE_EDGE_RISING 3
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#define SUN6I_NMI_BIT BIT(0)
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#define SUN6I_NMI_NEEDS_ACK ((void *)1)
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#define SUN6I_NR_TOP_LEVEL_IRQS 64
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#define SUN6I_NR_DIRECT_IRQS 16
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#define SUN6I_NR_MUX_BITS 128
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struct sun6i_r_intc_variant {
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u32 first_mux_irq;
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u32 nr_mux_irqs;
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u32 mux_valid[BITS_TO_U32(SUN6I_NR_MUX_BITS)];
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};
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static void __iomem *base;
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static irq_hw_number_t nmi_hwirq;
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static DECLARE_BITMAP(wake_irq_enabled, SUN6I_NR_TOP_LEVEL_IRQS);
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static DECLARE_BITMAP(wake_mux_enabled, SUN6I_NR_MUX_BITS);
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static DECLARE_BITMAP(wake_mux_valid, SUN6I_NR_MUX_BITS);
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static void sun6i_r_intc_ack_nmi(void)
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{
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writel_relaxed(SUN6I_NMI_BIT, base + SUN6I_IRQ_PENDING(0));
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}
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static void sun6i_r_intc_nmi_ack(struct irq_data *data)
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{
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if (irqd_get_trigger_type(data) & IRQ_TYPE_EDGE_BOTH)
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sun6i_r_intc_ack_nmi();
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else
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data->chip_data = SUN6I_NMI_NEEDS_ACK;
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}
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static void sun6i_r_intc_nmi_eoi(struct irq_data *data)
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{
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/* For oneshot IRQs, delay the ack until the IRQ is unmasked. */
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if (data->chip_data == SUN6I_NMI_NEEDS_ACK && !irqd_irq_masked(data)) {
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data->chip_data = NULL;
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sun6i_r_intc_ack_nmi();
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}
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irq_chip_eoi_parent(data);
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}
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static void sun6i_r_intc_nmi_unmask(struct irq_data *data)
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{
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if (data->chip_data == SUN6I_NMI_NEEDS_ACK) {
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data->chip_data = NULL;
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sun6i_r_intc_ack_nmi();
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}
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irq_chip_unmask_parent(data);
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}
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static int sun6i_r_intc_nmi_set_type(struct irq_data *data, unsigned int type)
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{
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u32 nmi_src_type;
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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nmi_src_type = SUN6I_NMI_SRC_TYPE_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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nmi_src_type = SUN6I_NMI_SRC_TYPE_EDGE_FALLING;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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nmi_src_type = SUN6I_NMI_SRC_TYPE_LEVEL_HIGH;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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nmi_src_type = SUN6I_NMI_SRC_TYPE_LEVEL_LOW;
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break;
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default:
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return -EINVAL;
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}
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writel_relaxed(nmi_src_type, base + SUN6I_NMI_CTRL);
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/*
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* The "External NMI" GIC input connects to a latch inside R_INTC, not
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* directly to the pin. So the GIC trigger type does not depend on the
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* NMI pin trigger type.
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*/
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return irq_chip_set_type_parent(data, IRQ_TYPE_LEVEL_HIGH);
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}
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static int sun6i_r_intc_nmi_set_irqchip_state(struct irq_data *data,
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enum irqchip_irq_state which,
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bool state)
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{
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if (which == IRQCHIP_STATE_PENDING && !state)
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sun6i_r_intc_ack_nmi();
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return irq_chip_set_parent_state(data, which, state);
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}
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static int sun6i_r_intc_irq_set_wake(struct irq_data *data, unsigned int on)
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{
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unsigned long offset_from_nmi = data->hwirq - nmi_hwirq;
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if (offset_from_nmi < SUN6I_NR_DIRECT_IRQS)
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assign_bit(offset_from_nmi, wake_irq_enabled, on);
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else if (test_bit(data->hwirq, wake_mux_valid))
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assign_bit(data->hwirq, wake_mux_enabled, on);
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else
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/* Not wakeup capable. */
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return -EPERM;
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return 0;
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}
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static struct irq_chip sun6i_r_intc_nmi_chip = {
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.name = "sun6i-r-intc",
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.irq_ack = sun6i_r_intc_nmi_ack,
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = sun6i_r_intc_nmi_unmask,
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.irq_eoi = sun6i_r_intc_nmi_eoi,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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.irq_set_type = sun6i_r_intc_nmi_set_type,
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.irq_set_irqchip_state = sun6i_r_intc_nmi_set_irqchip_state,
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.irq_set_wake = sun6i_r_intc_irq_set_wake,
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.flags = IRQCHIP_SET_TYPE_MASKED,
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};
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static struct irq_chip sun6i_r_intc_wakeup_chip = {
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.name = "sun6i-r-intc",
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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.irq_set_type = irq_chip_set_type_parent,
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.irq_set_wake = sun6i_r_intc_irq_set_wake,
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.flags = IRQCHIP_SET_TYPE_MASKED,
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};
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static int sun6i_r_intc_domain_translate(struct irq_domain *domain,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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/* Accept the old two-cell binding for the NMI only. */
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if (fwspec->param_count == 2 && fwspec->param[0] == 0) {
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*hwirq = nmi_hwirq;
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*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
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return 0;
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}
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/* Otherwise this binding should match the GIC SPI binding. */
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if (fwspec->param_count < 3)
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return -EINVAL;
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if (fwspec->param[0] != GIC_SPI)
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return -EINVAL;
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*hwirq = fwspec->param[1];
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*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
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return 0;
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}
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static int sun6i_r_intc_domain_alloc(struct irq_domain *domain,
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unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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struct irq_fwspec *fwspec = arg;
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struct irq_fwspec gic_fwspec;
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unsigned long hwirq;
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unsigned int type;
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int i, ret;
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ret = sun6i_r_intc_domain_translate(domain, fwspec, &hwirq, &type);
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if (ret)
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return ret;
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if (hwirq + nr_irqs > SUN6I_NR_MUX_BITS)
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return -EINVAL;
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/* Construct a GIC-compatible fwspec from this fwspec. */
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gic_fwspec = (struct irq_fwspec) {
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.fwnode = domain->parent->fwnode,
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.param_count = 3,
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.param = { GIC_SPI, hwirq, type },
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};
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ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_fwspec);
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if (ret)
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return ret;
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for (i = 0; i < nr_irqs; ++i, ++hwirq, ++virq) {
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if (hwirq == nmi_hwirq) {
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irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
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&sun6i_r_intc_nmi_chip, 0);
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irq_set_handler(virq, handle_fasteoi_ack_irq);
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} else {
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irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
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&sun6i_r_intc_wakeup_chip, 0);
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}
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}
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return 0;
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}
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static const struct irq_domain_ops sun6i_r_intc_domain_ops = {
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.translate = sun6i_r_intc_domain_translate,
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.alloc = sun6i_r_intc_domain_alloc,
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.free = irq_domain_free_irqs_common,
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};
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static int sun6i_r_intc_suspend(void)
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{
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u32 buf[BITS_TO_U32(max(SUN6I_NR_TOP_LEVEL_IRQS, SUN6I_NR_MUX_BITS))];
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int i;
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/* Wake IRQs are enabled during system sleep and shutdown. */
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bitmap_to_arr32(buf, wake_irq_enabled, SUN6I_NR_TOP_LEVEL_IRQS);
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for (i = 0; i < BITS_TO_U32(SUN6I_NR_TOP_LEVEL_IRQS); ++i)
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writel_relaxed(buf[i], base + SUN6I_IRQ_ENABLE(i));
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bitmap_to_arr32(buf, wake_mux_enabled, SUN6I_NR_MUX_BITS);
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for (i = 0; i < BITS_TO_U32(SUN6I_NR_MUX_BITS); ++i)
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writel_relaxed(buf[i], base + SUN6I_MUX_ENABLE(i));
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return 0;
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}
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static void sun6i_r_intc_resume(void)
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{
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int i;
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/* Only the NMI is relevant during normal operation. */
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writel_relaxed(SUN6I_NMI_BIT, base + SUN6I_IRQ_ENABLE(0));
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for (i = 1; i < BITS_TO_U32(SUN6I_NR_TOP_LEVEL_IRQS); ++i)
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writel_relaxed(0, base + SUN6I_IRQ_ENABLE(i));
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}
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static void sun6i_r_intc_shutdown(void)
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{
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sun6i_r_intc_suspend();
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}
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static struct syscore_ops sun6i_r_intc_syscore_ops = {
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.suspend = sun6i_r_intc_suspend,
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.resume = sun6i_r_intc_resume,
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.shutdown = sun6i_r_intc_shutdown,
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};
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static int __init sun6i_r_intc_init(struct device_node *node,
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struct device_node *parent,
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const struct sun6i_r_intc_variant *v)
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{
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struct irq_domain *domain, *parent_domain;
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struct of_phandle_args nmi_parent;
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int ret;
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/* Extract the NMI hwirq number from the OF node. */
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ret = of_irq_parse_one(node, 0, &nmi_parent);
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if (ret)
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return ret;
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if (nmi_parent.args_count < 3 ||
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nmi_parent.args[0] != GIC_SPI ||
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nmi_parent.args[2] != IRQ_TYPE_LEVEL_HIGH)
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return -EINVAL;
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nmi_hwirq = nmi_parent.args[1];
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bitmap_set(wake_irq_enabled, v->first_mux_irq, v->nr_mux_irqs);
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bitmap_from_arr32(wake_mux_valid, v->mux_valid, SUN6I_NR_MUX_BITS);
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parent_domain = irq_find_host(parent);
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if (!parent_domain) {
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pr_err("%pOF: Failed to obtain parent domain\n", node);
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return -ENXIO;
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}
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base = of_io_request_and_map(node, 0, NULL);
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if (IS_ERR(base)) {
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pr_err("%pOF: Failed to map MMIO region\n", node);
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return PTR_ERR(base);
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}
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domain = irq_domain_add_hierarchy(parent_domain, 0, 0, node,
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&sun6i_r_intc_domain_ops, NULL);
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if (!domain) {
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pr_err("%pOF: Failed to allocate domain\n", node);
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iounmap(base);
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return -ENOMEM;
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}
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register_syscore_ops(&sun6i_r_intc_syscore_ops);
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sun6i_r_intc_ack_nmi();
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sun6i_r_intc_resume();
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return 0;
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}
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static const struct sun6i_r_intc_variant sun6i_a31_r_intc_variant __initconst = {
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.first_mux_irq = 19,
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.nr_mux_irqs = 13,
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.mux_valid = { 0xffffffff, 0xfff80000, 0xffffffff, 0x0000000f },
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};
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static int __init sun6i_a31_r_intc_init(struct device_node *node,
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struct device_node *parent)
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{
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return sun6i_r_intc_init(node, parent, &sun6i_a31_r_intc_variant);
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}
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IRQCHIP_DECLARE(sun6i_a31_r_intc, "allwinner,sun6i-a31-r-intc", sun6i_a31_r_intc_init);
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static const struct sun6i_r_intc_variant sun50i_h6_r_intc_variant __initconst = {
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.first_mux_irq = 21,
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.nr_mux_irqs = 16,
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.mux_valid = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff },
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};
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static int __init sun50i_h6_r_intc_init(struct device_node *node,
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struct device_node *parent)
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{
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return sun6i_r_intc_init(node, parent, &sun50i_h6_r_intc_variant);
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}
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IRQCHIP_DECLARE(sun50i_h6_r_intc, "allwinner,sun50i-h6-r-intc", sun50i_h6_r_intc_init);
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