mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-26 06:04:14 +08:00
ba282daa91
This contains the following changes: * Overlay surface alpha is configured separately from the overlay. This prevents display glitches (configure and fill the overlay first, set alpha to a visible value next) * Added an ioctl for configuring transparency of the Overlay and graphics planes. Blend mode, colorkey mode and global alpha mode are supported. * Added an ioctl for setting the plane order. The overlay plance can be placed over or under the graphics plane. * Added an ioctl for setting and reading chip registers, with mask. * Updated copyright for 2007 [adaplas] * Coding style changes Signed-off-by: Raphael Assenat <raph@8d.com> Signed-off-by: Antonino Daplas <adaplas@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
196 lines
7.2 KiB
C
196 lines
7.2 KiB
C
#ifndef __REGS_2700G_
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#define __REGS_2700G_
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/* extern unsigned long virt_base_2700; */
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/* #define __REG_2700G(x) (*(volatile unsigned long*)((x)+virt_base_2700)) */
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#define __REG_2700G(x) ((x)+virt_base_2700)
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/* System Configuration Registers (0x0000_0000 0x0000_0010) */
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#define SYSCFG __REG_2700G(0x00000000)
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#define PFBASE __REG_2700G(0x00000004)
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#define PFCEIL __REG_2700G(0x00000008)
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#define POLLFLAG __REG_2700G(0x0000000c)
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#define SYSRST __REG_2700G(0x00000010)
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/* Interrupt Control Registers (0x0000_0014 0x0000_002F) */
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#define NINTPW __REG_2700G(0x00000014)
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#define MINTENABLE __REG_2700G(0x00000018)
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#define MINTSTAT __REG_2700G(0x0000001c)
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#define SINTENABLE __REG_2700G(0x00000020)
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#define SINTSTAT __REG_2700G(0x00000024)
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#define SINTCLR __REG_2700G(0x00000028)
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/* Clock Control Registers (0x0000_002C 0x0000_005F) */
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#define SYSCLKSRC __REG_2700G(0x0000002c)
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#define PIXCLKSRC __REG_2700G(0x00000030)
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#define CLKSLEEP __REG_2700G(0x00000034)
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#define COREPLL __REG_2700G(0x00000038)
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#define DISPPLL __REG_2700G(0x0000003c)
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#define PLLSTAT __REG_2700G(0x00000040)
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#define VOVRCLK __REG_2700G(0x00000044)
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#define PIXCLK __REG_2700G(0x00000048)
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#define MEMCLK __REG_2700G(0x0000004c)
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#define M24CLK __REG_2700G(0x00000050)
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#define MBXCLK __REG_2700G(0x00000054)
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#define SDCLK __REG_2700G(0x00000058)
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#define PIXCLKDIV __REG_2700G(0x0000005c)
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/* LCD Port Control Register (0x0000_0060 0x0000_006F) */
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#define LCD_CONFIG __REG_2700G(0x00000060)
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/* On-Die Frame Buffer Registers (0x0000_0064 0x0000_006B) */
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#define ODFBPWR __REG_2700G(0x00000064)
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#define ODFBSTAT __REG_2700G(0x00000068)
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/* GPIO Registers (0x0000_006C 0x0000_007F) */
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#define GPIOCGF __REG_2700G(0x0000006c)
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#define GPIOHI __REG_2700G(0x00000070)
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#define GPIOLO __REG_2700G(0x00000074)
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#define GPIOSTAT __REG_2700G(0x00000078)
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/* Pulse Width Modulator (PWM) Registers (0x0000_0200 0x0000_02FF) */
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#define PWMRST __REG_2700G(0x00000200)
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#define PWMCFG __REG_2700G(0x00000204)
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#define PWM0DIV __REG_2700G(0x00000210)
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#define PWM0DUTY __REG_2700G(0x00000214)
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#define PWM0PER __REG_2700G(0x00000218)
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#define PWM1DIV __REG_2700G(0x00000220)
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#define PWM1DUTY __REG_2700G(0x00000224)
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#define PWM1PER __REG_2700G(0x00000228)
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/* Identification (ID) Registers (0x0000_0300 0x0000_0FFF) */
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#define ID __REG_2700G(0x00000FF0)
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/* Local Memory (SDRAM) Interface Registers (0x0000_1000 0x0000_1FFF) */
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#define LMRST __REG_2700G(0x00001000)
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#define LMCFG __REG_2700G(0x00001004)
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#define LMPWR __REG_2700G(0x00001008)
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#define LMPWRSTAT __REG_2700G(0x0000100c)
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#define LMCEMR __REG_2700G(0x00001010)
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#define LMTYPE __REG_2700G(0x00001014)
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#define LMTIM __REG_2700G(0x00001018)
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#define LMREFRESH __REG_2700G(0x0000101c)
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#define LMPROTMIN __REG_2700G(0x00001020)
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#define LMPROTMAX __REG_2700G(0x00001024)
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#define LMPROTCFG __REG_2700G(0x00001028)
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#define LMPROTERR __REG_2700G(0x0000102c)
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/* Plane Controller Registers (0x0000_2000 0x0000_2FFF) */
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#define GSCTRL __REG_2700G(0x00002000)
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#define VSCTRL __REG_2700G(0x00002004)
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#define GBBASE __REG_2700G(0x00002020)
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#define VBBASE __REG_2700G(0x00002024)
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#define GDRCTRL __REG_2700G(0x00002040)
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#define VCMSK __REG_2700G(0x00002044)
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#define GSCADR __REG_2700G(0x00002060)
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#define VSCADR __REG_2700G(0x00002064)
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#define VUBASE __REG_2700G(0x00002084)
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#define VVBASE __REG_2700G(0x000020a4)
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#define GSADR __REG_2700G(0x000020c0)
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#define VSADR __REG_2700G(0x000020c4)
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#define HCCTRL __REG_2700G(0x00002100)
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#define HCSIZE __REG_2700G(0x00002110)
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#define HCPOS __REG_2700G(0x00002120)
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#define HCBADR __REG_2700G(0x00002130)
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#define HCCKMSK __REG_2700G(0x00002140)
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#define GPLUT __REG_2700G(0x00002150)
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#define DSCTRL __REG_2700G(0x00002154)
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#define DHT01 __REG_2700G(0x00002158)
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#define DHT02 __REG_2700G(0x0000215c)
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#define DHT03 __REG_2700G(0x00002160)
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#define DVT01 __REG_2700G(0x00002164)
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#define DVT02 __REG_2700G(0x00002168)
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#define DVT03 __REG_2700G(0x0000216c)
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#define DBCOL __REG_2700G(0x00002170)
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#define BGCOLOR __REG_2700G(0x00002174)
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#define DINTRS __REG_2700G(0x00002178)
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#define DINTRE __REG_2700G(0x0000217c)
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#define DINTRCNT __REG_2700G(0x00002180)
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#define DSIG __REG_2700G(0x00002184)
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#define DMCTRL __REG_2700G(0x00002188)
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#define CLIPCTRL __REG_2700G(0x0000218c)
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#define SPOCTRL __REG_2700G(0x00002190)
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#define SVCTRL __REG_2700G(0x00002194)
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/* 0x0000_2198 */
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/* 0x0000_21A8 VSCOEFF[0:4] Video Scalar Vertical Coefficient [0:4] 4.14.5 */
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#define VSCOEFF0 __REG_2700G(0x00002198)
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#define VSCOEFF1 __REG_2700G(0x0000219c)
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#define VSCOEFF2 __REG_2700G(0x000021a0)
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#define VSCOEFF3 __REG_2700G(0x000021a4)
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#define VSCOEFF4 __REG_2700G(0x000021a8)
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#define SHCTRL __REG_2700G(0x000021b0)
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/* 0x0000_21B4 */
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/* 0x0000_21D4 HSCOEFF[0:8] Video Scalar Horizontal Coefficient [0:8] 4.14.7 */
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#define HSCOEFF0 __REG_2700G(0x000021b4)
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#define HSCOEFF1 __REG_2700G(0x000021b8)
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#define HSCOEFF2 __REG_2700G(0x000021bc)
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#define HSCOEFF3 __REG_2700G(0x000021c0)
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#define HSCOEFF4 __REG_2700G(0x000021c4)
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#define HSCOEFF5 __REG_2700G(0x000021c8)
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#define HSCOEFF6 __REG_2700G(0x000021cc)
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#define HSCOEFF7 __REG_2700G(0x000021d0)
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#define HSCOEFF8 __REG_2700G(0x000021d4)
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#define SSSIZE __REG_2700G(0x000021D8)
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/* 0x0000_2200 */
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/* 0x0000_2240 VIDGAM[0:16] Video Gamma LUT Index [0:16] 4.15.2 */
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#define VIDGAM0 __REG_2700G(0x00002200)
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#define VIDGAM1 __REG_2700G(0x00002204)
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#define VIDGAM2 __REG_2700G(0x00002208)
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#define VIDGAM3 __REG_2700G(0x0000220c)
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#define VIDGAM4 __REG_2700G(0x00002210)
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#define VIDGAM5 __REG_2700G(0x00002214)
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#define VIDGAM6 __REG_2700G(0x00002218)
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#define VIDGAM7 __REG_2700G(0x0000221c)
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#define VIDGAM8 __REG_2700G(0x00002220)
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#define VIDGAM9 __REG_2700G(0x00002224)
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#define VIDGAM10 __REG_2700G(0x00002228)
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#define VIDGAM11 __REG_2700G(0x0000222c)
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#define VIDGAM12 __REG_2700G(0x00002230)
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#define VIDGAM13 __REG_2700G(0x00002234)
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#define VIDGAM14 __REG_2700G(0x00002238)
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#define VIDGAM15 __REG_2700G(0x0000223c)
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#define VIDGAM16 __REG_2700G(0x00002240)
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/* 0x0000_2250 */
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/* 0x0000_2290 GFXGAM[0:16] Graphics Gamma LUT Index [0:16] 4.15.3 */
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#define GFXGAM0 __REG_2700G(0x00002250)
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#define GFXGAM1 __REG_2700G(0x00002254)
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#define GFXGAM2 __REG_2700G(0x00002258)
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#define GFXGAM3 __REG_2700G(0x0000225c)
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#define GFXGAM4 __REG_2700G(0x00002260)
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#define GFXGAM5 __REG_2700G(0x00002264)
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#define GFXGAM6 __REG_2700G(0x00002268)
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#define GFXGAM7 __REG_2700G(0x0000226c)
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#define GFXGAM8 __REG_2700G(0x00002270)
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#define GFXGAM9 __REG_2700G(0x00002274)
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#define GFXGAM10 __REG_2700G(0x00002278)
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#define GFXGAM11 __REG_2700G(0x0000227c)
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#define GFXGAM12 __REG_2700G(0x00002280)
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#define GFXGAM13 __REG_2700G(0x00002284)
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#define GFXGAM14 __REG_2700G(0x00002288)
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#define GFXGAM15 __REG_2700G(0x0000228c)
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#define GFXGAM16 __REG_2700G(0x00002290)
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#define DLSTS __REG_2700G(0x00002300)
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#define DLLCTRL __REG_2700G(0x00002304)
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#define DVLNUM __REG_2700G(0x00002308)
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#define DUCTRL __REG_2700G(0x0000230c)
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#define DVECTRL __REG_2700G(0x00002310)
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#define DHDET __REG_2700G(0x00002314)
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#define DVDET __REG_2700G(0x00002318)
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#define DODMSK __REG_2700G(0x0000231c)
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#define CSC01 __REG_2700G(0x00002330)
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#define CSC02 __REG_2700G(0x00002334)
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#define CSC03 __REG_2700G(0x00002338)
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#define CSC04 __REG_2700G(0x0000233c)
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#define CSC05 __REG_2700G(0x00002340)
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#define FB_MEMORY_START __REG_2700G(0x00060000)
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#endif /* __REGS_2700G_ */
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