mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-21 11:44:01 +08:00
e7068ad337
More cosmetic cleanup:
- Replace 8-space indents by proper tab indents.
- In structure initialisers, use a trailing comma for every member.
- Collapse "},\n{" in structure initialiers to "}, {".
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <linux@arm.linux.org.uk>
315 lines
7.8 KiB
C
315 lines
7.8 KiB
C
/*
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* arch/arm/mach-orion5x/rd88f5182-setup.c
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*
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* Marvell Orion-NAS Reference Design Setup
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*
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* Maintainer: Ronen Shitrit <rshitrit@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mv643xx_eth.h>
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#include <linux/ata_platform.h>
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#include <linux/i2c.h>
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#include <asm/mach-types.h>
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#include <asm/gpio.h>
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#include <asm/leds.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/pci.h>
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#include <asm/arch/orion5x.h>
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#include "common.h"
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/*****************************************************************************
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* RD-88F5182 Info
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****************************************************************************/
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/*
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* 512K NOR flash Device bus boot chip select
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*/
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#define RD88F5182_NOR_BOOT_BASE 0xf4000000
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#define RD88F5182_NOR_BOOT_SIZE SZ_512K
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/*
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* 16M NOR flash on Device bus chip select 1
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*/
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#define RD88F5182_NOR_BASE 0xfc000000
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#define RD88F5182_NOR_SIZE SZ_16M
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/*
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* PCI
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*/
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#define RD88F5182_PCI_SLOT0_OFFS 7
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#define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7
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#define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6
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/*
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* GPIO Debug LED
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*/
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#define RD88F5182_GPIO_DBG_LED 0
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/*****************************************************************************
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* 16M NOR Flash on Device bus CS1
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****************************************************************************/
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static struct physmap_flash_data rd88f5182_nor_flash_data = {
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.width = 1,
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};
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static struct resource rd88f5182_nor_flash_resource = {
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.flags = IORESOURCE_MEM,
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.start = RD88F5182_NOR_BASE,
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.end = RD88F5182_NOR_BASE + RD88F5182_NOR_SIZE - 1,
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};
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static struct platform_device rd88f5182_nor_flash = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &rd88f5182_nor_flash_data,
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},
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.num_resources = 1,
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.resource = &rd88f5182_nor_flash_resource,
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};
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#ifdef CONFIG_LEDS
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/*****************************************************************************
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* Use GPIO debug led as CPU active indication
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****************************************************************************/
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static void rd88f5182_dbgled_event(led_event_t evt)
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{
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int val;
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if (evt == led_idle_end)
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val = 1;
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else if (evt == led_idle_start)
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val = 0;
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else
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return;
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gpio_set_value(RD88F5182_GPIO_DBG_LED, val);
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}
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static int __init rd88f5182_dbgled_init(void)
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{
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int pin;
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if (machine_is_rd88f5182()) {
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pin = RD88F5182_GPIO_DBG_LED;
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if (gpio_request(pin, "DBGLED") == 0) {
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if (gpio_direction_output(pin, 0) != 0) {
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printk(KERN_ERR "rd88f5182_dbgled_init failed "
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"to set output pin %d\n", pin);
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gpio_free(pin);
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return 0;
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}
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} else {
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printk(KERN_ERR "rd88f5182_dbgled_init failed "
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"to request gpio %d\n", pin);
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return 0;
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}
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leds_event = rd88f5182_dbgled_event;
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}
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return 0;
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}
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__initcall(rd88f5182_dbgled_init);
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#endif
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/*****************************************************************************
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* PCI
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****************************************************************************/
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void __init rd88f5182_pci_preinit(void)
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{
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int pin;
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/*
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* Configure PCI GPIO IRQ pins
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*/
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pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
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if (gpio_request(pin, "PCI IntA") == 0) {
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if (gpio_direction_input(pin) == 0) {
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set_irq_type(gpio_to_irq(pin), IRQT_LOW);
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} else {
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printk(KERN_ERR "rd88f5182_pci_preinit faield to "
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"set_irq_type pin %d\n", pin);
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gpio_free(pin);
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}
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} else {
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printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
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}
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pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
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if (gpio_request(pin, "PCI IntB") == 0) {
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if (gpio_direction_input(pin) == 0) {
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set_irq_type(gpio_to_irq(pin), IRQT_LOW);
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} else {
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printk(KERN_ERR "rd88f5182_pci_preinit faield to "
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"set_irq_type pin %d\n", pin);
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gpio_free(pin);
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}
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} else {
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printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
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}
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}
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static int __init rd88f5182_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq;
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/*
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* Check for devices with hard-wired IRQs.
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*/
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irq = orion5x_pci_map_irq(dev, slot, pin);
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if (irq != -1)
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return irq;
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/*
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* PCI IRQs are connected via GPIOs
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*/
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switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
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case 0:
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if (pin == 1)
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return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
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else
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return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
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default:
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return -1;
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}
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}
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static struct hw_pci rd88f5182_pci __initdata = {
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.nr_controllers = 2,
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.preinit = rd88f5182_pci_preinit,
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.swizzle = pci_std_swizzle,
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.setup = orion5x_pci_sys_setup,
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.scan = orion5x_pci_sys_scan_bus,
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.map_irq = rd88f5182_pci_map_irq,
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};
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static int __init rd88f5182_pci_init(void)
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{
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if (machine_is_rd88f5182())
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pci_common_init(&rd88f5182_pci);
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return 0;
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}
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subsys_initcall(rd88f5182_pci_init);
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/*****************************************************************************
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* Ethernet
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****************************************************************************/
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static struct mv643xx_eth_platform_data rd88f5182_eth_data = {
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.phy_addr = 8,
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.force_phy_addr = 1,
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};
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/*****************************************************************************
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* RTC DS1338 on I2C bus
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****************************************************************************/
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static struct i2c_board_info __initdata rd88f5182_i2c_rtc = {
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I2C_BOARD_INFO("ds1338", 0x68),
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};
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/*****************************************************************************
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* Sata
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****************************************************************************/
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static struct mv_sata_platform_data rd88f5182_sata_data = {
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.n_ports = 2,
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};
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/*****************************************************************************
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* General Setup
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****************************************************************************/
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static struct platform_device *rd88f5182_devices[] __initdata = {
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&rd88f5182_nor_flash,
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};
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static void __init rd88f5182_init(void)
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{
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/*
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* Setup basic Orion functions. Need to be called early.
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*/
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orion5x_init();
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/*
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* Setup the CPU address decode windows for our devices
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*/
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orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE,
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RD88F5182_NOR_BOOT_SIZE);
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orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
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/*
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* Open a special address decode windows for the PCIe WA.
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*/
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orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
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ORION5X_PCIE_WA_SIZE);
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/*
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* Setup Multiplexing Pins --
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* MPP[0] Debug Led (GPIO - Out)
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* MPP[1] Debug Led (GPIO - Out)
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* MPP[2] N/A
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* MPP[3] RTC_Int (GPIO - In)
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* MPP[4] GPIO
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* MPP[5] GPIO
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* MPP[6] PCI_intA (GPIO - In)
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* MPP[7] PCI_intB (GPIO - In)
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* MPP[8-11] N/A
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* MPP[12] SATA 0 presence Indication
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* MPP[13] SATA 1 presence Indication
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* MPP[14] SATA 0 active Indication
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* MPP[15] SATA 1 active indication
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* MPP[16-19] Not used
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* MPP[20] PCI Clock to MV88F5182
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* MPP[21] PCI Clock to mini PCI CON11
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* MPP[22] USB 0 over current indication
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* MPP[23] USB 1 over current indication
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* MPP[24] USB 1 over current enable
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* MPP[25] USB 0 over current enable
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*/
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orion5x_write(MPP_0_7_CTRL, 0x00000003);
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orion5x_write(MPP_8_15_CTRL, 0x55550000);
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orion5x_write(MPP_16_19_CTRL, 0x5555);
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orion5x_gpio_set_valid_pins(0x000000fb);
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platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices));
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i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
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orion5x_eth_init(&rd88f5182_eth_data);
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orion5x_sata_init(&rd88f5182_sata_data);
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}
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MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
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/* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
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.phys_io = ORION5X_REGS_PHYS_BASE,
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.io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
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.boot_params = 0x00000100,
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.init_machine = rd88f5182_init,
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.map_io = orion5x_map_io,
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.init_irq = orion5x_init_irq,
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.timer = &orion5x_timer,
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MACHINE_END
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