mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-23 12:43:55 +08:00
588ab3f9af
- Initial page table creation reworked to avoid breaking large block mappings (huge pages) into smaller ones. The ARM architecture requires break-before-make in such cases to avoid TLB conflicts but that's not always possible on live page tables - Kernel virtual memory layout: the kernel image is no longer linked to the bottom of the linear mapping (PAGE_OFFSET) but at the bottom of the vmalloc space, allowing the kernel to be loaded (nearly) anywhere in physical RAM - Kernel ASLR: position independent kernel Image and modules being randomly mapped in the vmalloc space with the randomness is provided by UEFI (efi_get_random_bytes() patches merged via the arm64 tree, acked by Matt Fleming) - Implement relative exception tables for arm64, required by KASLR (initial code for ARCH_HAS_RELATIVE_EXTABLE added to lib/extable.c but actual x86 conversion to deferred to 4.7 because of the merge dependencies) - Support for the User Access Override feature of ARMv8.2: this allows uaccess functions (get_user etc.) to be implemented using LDTR/STTR instructions. Such instructions, when run by the kernel, perform unprivileged accesses adding an extra level of protection. The set_fs() macro is used to "upgrade" such instruction to privileged accesses via the UAO bit - Half-precision floating point support (part of ARMv8.2) - Optimisations for CPUs with or without a hardware prefetcher (using run-time code patching) - copy_page performance improvement to deal with 128 bytes at a time - Sanity checks on the CPU capabilities (via CPUID) to prevent incompatible secondary CPUs from being brought up (e.g. weird big.LITTLE configurations) - valid_user_regs() reworked for better sanity check of the sigcontext information (restored pstate information) - ACPI parking protocol implementation - CONFIG_DEBUG_RODATA enabled by default - VDSO code marked as read-only - DEBUG_PAGEALLOC support - ARCH_HAS_UBSAN_SANITIZE_ALL enabled - Erratum workaround Cavium ThunderX SoC - set_pte_at() fix for PROT_NONE mappings - Code clean-ups -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJW6u95AAoJEGvWsS0AyF7xMyoP/3x2O6bgreSQ84BdO4JChN4+ RQ9OVdX8u2ItO9sgaCY2AA6KoiBuEjGmPl/XRuK0I7DpODTtRjEXQHuNNhz8AelC hn4AEVqamY6Z5BzHFIjs8G9ydEbq+OXcKWEdwSsBhP/cMvI7ss3dps1f5iNPT5Vv 50E/kUz+aWYy7pKlB18VDV7TUOA3SuYuGknWV8+bOY5uPb8hNT3Y3fHOg/EuNNN3 DIuYH1V7XQkXtF+oNVIGxzzJCXULBE7egMcWAm1ydSOHK0JwkZAiL7OhI7ceVD0x YlDxBnqmi4cgzfBzTxITAhn3OParwN6udQprdF1WGtFF6fuY2eRDSH/L/iZoE4DY OulL951OsBtF8YC3+RKLk908/0bA2Uw8ftjCOFJTYbSnZBj1gWK41VkCYMEXiHQk EaN8+2Iw206iYIoyvdjGCLw7Y0oakDoVD9vmv12SOaHeQljTkjoN8oIlfjjKTeP7 3AXj5v9BDMDVh40nkVayysRNvqe48Kwt9Wn0rhVTLxwdJEiFG/OIU6HLuTkretdN dcCNFSQrRieSFHpBK9G0vKIpIss1ZwLm8gjocVXH7VK4Mo/TNQe4p2/wAF29mq4r xu1UiXmtU3uWxiqZnt72LOYFCarQ0sFA5+pMEvF5W+NrVB0wGpXhcwm+pGsIi4IM LepccTgykiUBqW5TRzPz =/oS+ -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 updates from Catalin Marinas: "Here are the main arm64 updates for 4.6. There are some relatively intrusive changes to support KASLR, the reworking of the kernel virtual memory layout and initial page table creation. Summary: - Initial page table creation reworked to avoid breaking large block mappings (huge pages) into smaller ones. The ARM architecture requires break-before-make in such cases to avoid TLB conflicts but that's not always possible on live page tables - Kernel virtual memory layout: the kernel image is no longer linked to the bottom of the linear mapping (PAGE_OFFSET) but at the bottom of the vmalloc space, allowing the kernel to be loaded (nearly) anywhere in physical RAM - Kernel ASLR: position independent kernel Image and modules being randomly mapped in the vmalloc space with the randomness is provided by UEFI (efi_get_random_bytes() patches merged via the arm64 tree, acked by Matt Fleming) - Implement relative exception tables for arm64, required by KASLR (initial code for ARCH_HAS_RELATIVE_EXTABLE added to lib/extable.c but actual x86 conversion to deferred to 4.7 because of the merge dependencies) - Support for the User Access Override feature of ARMv8.2: this allows uaccess functions (get_user etc.) to be implemented using LDTR/STTR instructions. Such instructions, when run by the kernel, perform unprivileged accesses adding an extra level of protection. The set_fs() macro is used to "upgrade" such instruction to privileged accesses via the UAO bit - Half-precision floating point support (part of ARMv8.2) - Optimisations for CPUs with or without a hardware prefetcher (using run-time code patching) - copy_page performance improvement to deal with 128 bytes at a time - Sanity checks on the CPU capabilities (via CPUID) to prevent incompatible secondary CPUs from being brought up (e.g. weird big.LITTLE configurations) - valid_user_regs() reworked for better sanity check of the sigcontext information (restored pstate information) - ACPI parking protocol implementation - CONFIG_DEBUG_RODATA enabled by default - VDSO code marked as read-only - DEBUG_PAGEALLOC support - ARCH_HAS_UBSAN_SANITIZE_ALL enabled - Erratum workaround Cavium ThunderX SoC - set_pte_at() fix for PROT_NONE mappings - Code clean-ups" * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (99 commits) arm64: kasan: Fix zero shadow mapping overriding kernel image shadow arm64: kasan: Use actual memory node when populating the kernel image shadow arm64: Update PTE_RDONLY in set_pte_at() for PROT_NONE permission arm64: Fix misspellings in comments. arm64: efi: add missing frame pointer assignment arm64: make mrs_s prefixing implicit in read_cpuid arm64: enable CONFIG_DEBUG_RODATA by default arm64: Rework valid_user_regs arm64: mm: check at build time that PAGE_OFFSET divides the VA space evenly arm64: KVM: Move kvm_call_hyp back to its original localtion arm64: mm: treat memstart_addr as a signed quantity arm64: mm: list kernel sections in order arm64: lse: deal with clobbered IP registers after branch via PLT arm64: mm: dump: Use VA_START directly instead of private LOWEST_ADDR arm64: kconfig: add submenu for 8.2 architectural features arm64: kernel: acpi: fix ioremap in ACPI parking protocol cpu_postboot arm64: Add support for Half precision floating point arm64: Remove fixmap include fragility arm64: Add workaround for Cavium erratum 27456 arm64: mm: Mark .rodata as RO ...
430 lines
9.8 KiB
C
430 lines
9.8 KiB
C
/*
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* ARMv8 single-step debug support and mdscr context switching.
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*
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* Copyright (C) 2012 ARM Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Author: Will Deacon <will.deacon@arm.com>
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*/
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#include <linux/cpu.h>
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#include <linux/debugfs.h>
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#include <linux/hardirq.h>
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#include <linux/init.h>
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#include <linux/ptrace.h>
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#include <linux/stat.h>
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#include <linux/uaccess.h>
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#include <asm/cpufeature.h>
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#include <asm/cputype.h>
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#include <asm/debug-monitors.h>
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#include <asm/system_misc.h>
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/* Determine debug architecture. */
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u8 debug_monitors_arch(void)
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{
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return cpuid_feature_extract_unsigned_field(read_system_reg(SYS_ID_AA64DFR0_EL1),
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ID_AA64DFR0_DEBUGVER_SHIFT);
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}
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/*
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* MDSCR access routines.
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*/
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static void mdscr_write(u32 mdscr)
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{
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unsigned long flags;
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local_dbg_save(flags);
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asm volatile("msr mdscr_el1, %0" :: "r" (mdscr));
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local_dbg_restore(flags);
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}
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static u32 mdscr_read(void)
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{
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u32 mdscr;
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asm volatile("mrs %0, mdscr_el1" : "=r" (mdscr));
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return mdscr;
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}
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/*
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* Allow root to disable self-hosted debug from userspace.
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* This is useful if you want to connect an external JTAG debugger.
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*/
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static bool debug_enabled = true;
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static int create_debug_debugfs_entry(void)
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{
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debugfs_create_bool("debug_enabled", 0644, NULL, &debug_enabled);
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return 0;
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}
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fs_initcall(create_debug_debugfs_entry);
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static int __init early_debug_disable(char *buf)
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{
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debug_enabled = false;
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return 0;
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}
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early_param("nodebugmon", early_debug_disable);
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/*
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* Keep track of debug users on each core.
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* The ref counts are per-cpu so we use a local_t type.
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*/
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static DEFINE_PER_CPU(int, mde_ref_count);
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static DEFINE_PER_CPU(int, kde_ref_count);
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void enable_debug_monitors(enum dbg_active_el el)
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{
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u32 mdscr, enable = 0;
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WARN_ON(preemptible());
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if (this_cpu_inc_return(mde_ref_count) == 1)
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enable = DBG_MDSCR_MDE;
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if (el == DBG_ACTIVE_EL1 &&
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this_cpu_inc_return(kde_ref_count) == 1)
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enable |= DBG_MDSCR_KDE;
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if (enable && debug_enabled) {
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mdscr = mdscr_read();
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mdscr |= enable;
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mdscr_write(mdscr);
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}
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}
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void disable_debug_monitors(enum dbg_active_el el)
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{
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u32 mdscr, disable = 0;
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WARN_ON(preemptible());
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if (this_cpu_dec_return(mde_ref_count) == 0)
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disable = ~DBG_MDSCR_MDE;
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if (el == DBG_ACTIVE_EL1 &&
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this_cpu_dec_return(kde_ref_count) == 0)
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disable &= ~DBG_MDSCR_KDE;
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if (disable) {
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mdscr = mdscr_read();
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mdscr &= disable;
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mdscr_write(mdscr);
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}
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}
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/*
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* OS lock clearing.
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*/
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static void clear_os_lock(void *unused)
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{
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asm volatile("msr oslar_el1, %0" : : "r" (0));
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}
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static int os_lock_notify(struct notifier_block *self,
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unsigned long action, void *data)
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{
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int cpu = (unsigned long)data;
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if ((action & ~CPU_TASKS_FROZEN) == CPU_ONLINE)
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smp_call_function_single(cpu, clear_os_lock, NULL, 1);
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return NOTIFY_OK;
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}
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static struct notifier_block os_lock_nb = {
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.notifier_call = os_lock_notify,
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};
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static int debug_monitors_init(void)
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{
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cpu_notifier_register_begin();
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/* Clear the OS lock. */
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on_each_cpu(clear_os_lock, NULL, 1);
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isb();
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local_dbg_enable();
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/* Register hotplug handler. */
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__register_cpu_notifier(&os_lock_nb);
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cpu_notifier_register_done();
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return 0;
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}
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postcore_initcall(debug_monitors_init);
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/*
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* Single step API and exception handling.
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*/
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static void set_regs_spsr_ss(struct pt_regs *regs)
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{
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unsigned long spsr;
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spsr = regs->pstate;
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spsr &= ~DBG_SPSR_SS;
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spsr |= DBG_SPSR_SS;
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regs->pstate = spsr;
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}
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static void clear_regs_spsr_ss(struct pt_regs *regs)
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{
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unsigned long spsr;
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spsr = regs->pstate;
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spsr &= ~DBG_SPSR_SS;
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regs->pstate = spsr;
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}
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/* EL1 Single Step Handler hooks */
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static LIST_HEAD(step_hook);
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static DEFINE_SPINLOCK(step_hook_lock);
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void register_step_hook(struct step_hook *hook)
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{
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spin_lock(&step_hook_lock);
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list_add_rcu(&hook->node, &step_hook);
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spin_unlock(&step_hook_lock);
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}
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void unregister_step_hook(struct step_hook *hook)
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{
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spin_lock(&step_hook_lock);
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list_del_rcu(&hook->node);
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spin_unlock(&step_hook_lock);
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synchronize_rcu();
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}
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/*
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* Call registered single step handlers
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* There is no Syndrome info to check for determining the handler.
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* So we call all the registered handlers, until the right handler is
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* found which returns zero.
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*/
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static int call_step_hook(struct pt_regs *regs, unsigned int esr)
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{
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struct step_hook *hook;
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int retval = DBG_HOOK_ERROR;
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rcu_read_lock();
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list_for_each_entry_rcu(hook, &step_hook, node) {
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retval = hook->fn(regs, esr);
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if (retval == DBG_HOOK_HANDLED)
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break;
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}
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rcu_read_unlock();
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return retval;
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}
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static void send_user_sigtrap(int si_code)
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{
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struct pt_regs *regs = current_pt_regs();
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siginfo_t info = {
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.si_signo = SIGTRAP,
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.si_errno = 0,
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.si_code = si_code,
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.si_addr = (void __user *)instruction_pointer(regs),
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};
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if (WARN_ON(!user_mode(regs)))
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return;
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if (interrupts_enabled(regs))
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local_irq_enable();
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force_sig_info(SIGTRAP, &info, current);
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}
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static int single_step_handler(unsigned long addr, unsigned int esr,
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struct pt_regs *regs)
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{
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/*
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* If we are stepping a pending breakpoint, call the hw_breakpoint
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* handler first.
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*/
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if (!reinstall_suspended_bps(regs))
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return 0;
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if (user_mode(regs)) {
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send_user_sigtrap(TRAP_HWBKPT);
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/*
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* ptrace will disable single step unless explicitly
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* asked to re-enable it. For other clients, it makes
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* sense to leave it enabled (i.e. rewind the controls
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* to the active-not-pending state).
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*/
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user_rewind_single_step(current);
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} else {
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if (call_step_hook(regs, esr) == DBG_HOOK_HANDLED)
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return 0;
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pr_warning("Unexpected kernel single-step exception at EL1\n");
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/*
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* Re-enable stepping since we know that we will be
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* returning to regs.
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*/
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set_regs_spsr_ss(regs);
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}
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return 0;
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}
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/*
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* Breakpoint handler is re-entrant as another breakpoint can
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* hit within breakpoint handler, especically in kprobes.
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* Use reader/writer locks instead of plain spinlock.
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*/
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static LIST_HEAD(break_hook);
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static DEFINE_SPINLOCK(break_hook_lock);
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void register_break_hook(struct break_hook *hook)
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{
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spin_lock(&break_hook_lock);
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list_add_rcu(&hook->node, &break_hook);
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spin_unlock(&break_hook_lock);
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}
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void unregister_break_hook(struct break_hook *hook)
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{
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spin_lock(&break_hook_lock);
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list_del_rcu(&hook->node);
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spin_unlock(&break_hook_lock);
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synchronize_rcu();
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}
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static int call_break_hook(struct pt_regs *regs, unsigned int esr)
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{
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struct break_hook *hook;
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int (*fn)(struct pt_regs *regs, unsigned int esr) = NULL;
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rcu_read_lock();
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list_for_each_entry_rcu(hook, &break_hook, node)
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if ((esr & hook->esr_mask) == hook->esr_val)
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fn = hook->fn;
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rcu_read_unlock();
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return fn ? fn(regs, esr) : DBG_HOOK_ERROR;
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}
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static int brk_handler(unsigned long addr, unsigned int esr,
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struct pt_regs *regs)
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{
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if (user_mode(regs)) {
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send_user_sigtrap(TRAP_BRKPT);
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} else if (call_break_hook(regs, esr) != DBG_HOOK_HANDLED) {
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pr_warning("Unexpected kernel BRK exception at EL1\n");
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return -EFAULT;
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}
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return 0;
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}
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int aarch32_break_handler(struct pt_regs *regs)
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{
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u32 arm_instr;
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u16 thumb_instr;
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bool bp = false;
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void __user *pc = (void __user *)instruction_pointer(regs);
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if (!compat_user_mode(regs))
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return -EFAULT;
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if (compat_thumb_mode(regs)) {
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/* get 16-bit Thumb instruction */
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get_user(thumb_instr, (u16 __user *)pc);
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thumb_instr = le16_to_cpu(thumb_instr);
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if (thumb_instr == AARCH32_BREAK_THUMB2_LO) {
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/* get second half of 32-bit Thumb-2 instruction */
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get_user(thumb_instr, (u16 __user *)(pc + 2));
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thumb_instr = le16_to_cpu(thumb_instr);
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bp = thumb_instr == AARCH32_BREAK_THUMB2_HI;
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} else {
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bp = thumb_instr == AARCH32_BREAK_THUMB;
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}
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} else {
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/* 32-bit ARM instruction */
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get_user(arm_instr, (u32 __user *)pc);
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arm_instr = le32_to_cpu(arm_instr);
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bp = (arm_instr & ~0xf0000000) == AARCH32_BREAK_ARM;
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}
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if (!bp)
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return -EFAULT;
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send_user_sigtrap(TRAP_BRKPT);
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return 0;
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}
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static int __init debug_traps_init(void)
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{
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hook_debug_fault_code(DBG_ESR_EVT_HWSS, single_step_handler, SIGTRAP,
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TRAP_HWBKPT, "single-step handler");
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hook_debug_fault_code(DBG_ESR_EVT_BRK, brk_handler, SIGTRAP,
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TRAP_BRKPT, "ptrace BRK handler");
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return 0;
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}
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arch_initcall(debug_traps_init);
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/* Re-enable single step for syscall restarting. */
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void user_rewind_single_step(struct task_struct *task)
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{
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/*
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* If single step is active for this thread, then set SPSR.SS
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* to 1 to avoid returning to the active-pending state.
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*/
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if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP))
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set_regs_spsr_ss(task_pt_regs(task));
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}
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void user_fastforward_single_step(struct task_struct *task)
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{
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if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP))
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clear_regs_spsr_ss(task_pt_regs(task));
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}
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/* Kernel API */
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void kernel_enable_single_step(struct pt_regs *regs)
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{
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WARN_ON(!irqs_disabled());
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set_regs_spsr_ss(regs);
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mdscr_write(mdscr_read() | DBG_MDSCR_SS);
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enable_debug_monitors(DBG_ACTIVE_EL1);
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}
|
|
|
|
void kernel_disable_single_step(void)
|
|
{
|
|
WARN_ON(!irqs_disabled());
|
|
mdscr_write(mdscr_read() & ~DBG_MDSCR_SS);
|
|
disable_debug_monitors(DBG_ACTIVE_EL1);
|
|
}
|
|
|
|
int kernel_active_single_step(void)
|
|
{
|
|
WARN_ON(!irqs_disabled());
|
|
return mdscr_read() & DBG_MDSCR_SS;
|
|
}
|
|
|
|
/* ptrace API */
|
|
void user_enable_single_step(struct task_struct *task)
|
|
{
|
|
set_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP);
|
|
set_regs_spsr_ss(task_pt_regs(task));
|
|
}
|
|
|
|
void user_disable_single_step(struct task_struct *task)
|
|
{
|
|
clear_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP);
|
|
}
|