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e7347a8683
This moves the definition of the default security feature flags (i.e., enabled by default) closer to the security feature flags. This can be used to restore current flags to the default flags. Signed-off-by: Mauricio Faria de Oliveira <mauricfo@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
75 lines
2.1 KiB
C
75 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Security related feature bit definitions.
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*
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* Copyright 2018, Michael Ellerman, IBM Corporation.
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*/
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#ifndef _ASM_POWERPC_SECURITY_FEATURES_H
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#define _ASM_POWERPC_SECURITY_FEATURES_H
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extern unsigned long powerpc_security_features;
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extern bool rfi_flush;
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static inline void security_ftr_set(unsigned long feature)
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{
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powerpc_security_features |= feature;
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}
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static inline void security_ftr_clear(unsigned long feature)
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{
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powerpc_security_features &= ~feature;
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}
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static inline bool security_ftr_enabled(unsigned long feature)
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{
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return !!(powerpc_security_features & feature);
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}
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// Features indicating support for Spectre/Meltdown mitigations
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// The L1-D cache can be flushed with ori r30,r30,0
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#define SEC_FTR_L1D_FLUSH_ORI30 0x0000000000000001ull
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// The L1-D cache can be flushed with mtspr 882,r0 (aka SPRN_TRIG2)
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#define SEC_FTR_L1D_FLUSH_TRIG2 0x0000000000000002ull
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// ori r31,r31,0 acts as a speculation barrier
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#define SEC_FTR_SPEC_BAR_ORI31 0x0000000000000004ull
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// Speculation past bctr is disabled
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#define SEC_FTR_BCCTRL_SERIALISED 0x0000000000000008ull
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// Entries in L1-D are private to a SMT thread
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#define SEC_FTR_L1D_THREAD_PRIV 0x0000000000000010ull
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// Indirect branch prediction cache disabled
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#define SEC_FTR_COUNT_CACHE_DISABLED 0x0000000000000020ull
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// Features indicating need for Spectre/Meltdown mitigations
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// The L1-D cache should be flushed on MSR[HV] 1->0 transition (hypervisor to guest)
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#define SEC_FTR_L1D_FLUSH_HV 0x0000000000000040ull
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// The L1-D cache should be flushed on MSR[PR] 0->1 transition (kernel to userspace)
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#define SEC_FTR_L1D_FLUSH_PR 0x0000000000000080ull
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// A speculation barrier should be used for bounds checks (Spectre variant 1)
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#define SEC_FTR_BNDS_CHK_SPEC_BAR 0x0000000000000100ull
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// Firmware configuration indicates user favours security over performance
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#define SEC_FTR_FAVOUR_SECURITY 0x0000000000000200ull
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// Features enabled by default
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#define SEC_FTR_DEFAULT \
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(SEC_FTR_L1D_FLUSH_HV | \
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SEC_FTR_L1D_FLUSH_PR | \
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SEC_FTR_BNDS_CHK_SPEC_BAR | \
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SEC_FTR_FAVOUR_SECURITY)
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#endif /* _ASM_POWERPC_SECURITY_FEATURES_H */
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