Zdenko Pulitika e53f21c761 clk: pistachio: Fix override of clk-pll settings from boot loader ... PLL enable callbacks are overriding PLL mode (int/frac) and Noise reduction (on/off) settings set by the boot loader which results in the incorrect clock rate. PLL mode and noise reduction are defined by the DSMPD and DACPD bits of the PLL control register. PLL .enable() callbacks enable PLL by deasserting all power-down bits of the PLL control register, including DSMPD and DACPD bits, which is not necessary since these bits don't actually enable/disable PLL. This commit fixes the problem by removing DSMPD and DACPD bits from the "PLL enable" mask. Fixes: 43049b0c83f17("CLK: Pistachio: Add PLL driver") Cc: <stable@vger.kernel.org> # 4.1 Reviewed-by: Andrew Bresitcker <abrestic@chromium.org> Signed-off-by: Zdenko Pulitika <zdenko.pulitika@imgtec.com> Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>		2015-08-26 11:34:34 -07:00
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clk-pistachio.c	CLK: Pistachio: Register external clock gates	2015-03-31 11:59:31 +02:00
clk-pll.c	clk: pistachio: Fix override of clk-pll settings from boot loader	2015-08-26 11:34:34 -07:00
clk.c	clk: pistachio: Include clk.h	2015-07-20 11:11:37 -07:00
clk.h	clk: pistachio: Fix 32bit integer overflows	2015-08-26 11:34:28 -07:00
Makefile	CLK: Pistachio: Register core clocks	2015-03-31 11:59:10 +02:00