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Commit 8c8a777 (ARM: OMAP2+: Add function to read GPMC settings from device-tree) added a device-tree property "gpmc,device-nand" to indicate is the GPMC child device is NAND. This commit should have updated the GPMC NAND documentation (Documentation/devicetree/bindings/mtd/gpmc-nand.txt) to list the property "gpmc,device-nand" as a required property and also updated the example. However, this property is redundant and not needed because the GPMC child device node for NAND is called "nand". Therefore, remove this property. Signed-off-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
131 lines
5.0 KiB
Plaintext
131 lines
5.0 KiB
Plaintext
Device tree bindings for OMAP general purpose memory controllers (GPMC)
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The actual devices are instantiated from the child nodes of a GPMC node.
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Required properties:
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- compatible: Should be set to one of the following:
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ti,omap2420-gpmc (omap2420)
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ti,omap2430-gpmc (omap2430)
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ti,omap3430-gpmc (omap3430 & omap3630)
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ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
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ti,am3352-gpmc (am335x devices)
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- reg: A resource specifier for the register space
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(see the example below)
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- ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
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completed.
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- #address-cells: Must be set to 2 to allow memory address translation
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- #size-cells: Must be set to 1 to allow CS address passing
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- gpmc,num-cs: The maximum number of chip-select lines that controller
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can support.
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- gpmc,num-waitpins: The maximum number of wait pins that controller can
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support.
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- ranges: Must be set up to reflect the memory layout with four
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integer values for each chip-select line in use:
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<cs-number> 0 <physical address of mapping> <size>
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Currently, calculated values derived from the contents
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of the per-CS register GPMC_CONFIG7 (as set up by the
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bootloader) are used for the physical address decoding.
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As this will change in the future, filling correct
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values here is a requirement.
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Timing properties for child nodes. All are optional and default to 0.
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- gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds
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Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2:
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- gpmc,cs-on-ns: Assertion time
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- gpmc,cs-rd-off-ns: Read deassertion time
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- gpmc,cs-wr-off-ns: Write deassertion time
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ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3:
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- gpmc,adv-on-ns: Assertion time
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- gpmc,adv-rd-off-ns: Read deassertion time
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- gpmc,adv-wr-off-ns: Write deassertion time
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WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
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- gpmc,we-on-ns Assertion time
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- gpmc,we-off-ns: Deassertion time
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OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
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- gpmc,oe-on-ns: Assertion time
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- gpmc,oe-off-ns: Deassertion time
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Access time and cycle time timings (in nanoseconds) corresponding to
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GPMC_CONFIG5:
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- gpmc,page-burst-access-ns: Multiple access word delay
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- gpmc,access-ns: Start-cycle to first data valid delay
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- gpmc,rd-cycle-ns: Total read cycle time
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- gpmc,wr-cycle-ns: Total write cycle time
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- gpmc,bus-turnaround-ns: Turn-around time between successive accesses
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- gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses
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- gpmc,clk-activation-ns: GPMC clock activation time
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- gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid
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data
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Boolean timing parameters. If property is present parameter enabled and
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disabled if omitted:
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- gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock
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- gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock
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- gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive
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accesses to a different CS
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- gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive
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accesses to the same CS
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- gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock
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- gpmc,we-extra-delay: WE signal is delayed by half GPMC clock
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- gpmc,time-para-granularity: Multiply all access times by 2
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The following are only applicable to OMAP3+ and AM335x:
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- gpmc,wr-access-ns: In synchronous write mode, for single or
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burst accesses, defines the number of
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GPMC_FCLK cycles from start access time
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to the GPMC_CLK rising edge used by the
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memory device for the first data capture.
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- gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies
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the time when the first data is driven on
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the address-data bus.
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GPMC chip-select settings properties for child nodes. All are optional.
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- gpmc,burst-length Page/burst length. Must be 4, 8 or 16.
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- gpmc,burst-wrap Enables wrap bursting
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- gpmc,burst-read Enables read page/burst mode
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- gpmc,burst-write Enables write page/burst mode
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- gpmc,device-width Total width of device(s) connected to a GPMC
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chip-select in bytes. The GPMC supports 8-bit
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and 16-bit devices and so this property must be
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1 or 2.
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- gpmc,mux-add-data Address and data multiplexing configuration.
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Valid values are 1 for address-address-data
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multiplexing mode and 2 for address-data
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multiplexing mode.
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- gpmc,sync-read Enables synchronous read. Defaults to asynchronous
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is this is not set.
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- gpmc,sync-write Enables synchronous writes. Defaults to asynchronous
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is this is not set.
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- gpmc,wait-pin Wait-pin used by client. Must be less than
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"gpmc,num-waitpins".
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- gpmc,wait-on-read Enables wait monitoring on reads.
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- gpmc,wait-on-write Enables wait monitoring on writes.
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Example for an AM33xx board:
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gpmc: gpmc@50000000 {
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compatible = "ti,am3352-gpmc";
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ti,hwmods = "gpmc";
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reg = <0x50000000 0x2000>;
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interrupts = <100>;
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gpmc,num-cs = <8>;
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gpmc,num-waitpins = <2>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
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/* child nodes go here */
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};
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