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3b57de958e
This patch adds and modifies code to support multiple Multicast and Unicast Synopsys MAC filter configurations. The default configuration is defined to support legacy driver behavior, which is 64 Multicast bins. The Unicast filter code previously assumed all controllers support 32 or 16 Unicast addresses based on controller version number, but this has been corrected to support a default of 1 Unicast address. The filter configuration may be specified through the devicetree using a Synopsys specific device tree entry. This information was verified with Synopsys through Synopsys Support Case #8000684337 and shared with the maintainer. Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
268 lines
10 KiB
C
268 lines
10 KiB
C
/*******************************************************************************
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#ifndef __DWMAC1000_H__
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#define __DWMAC1000_H__
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#include <linux/phy.h>
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#include "common.h"
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#define GMAC_CONTROL 0x00000000 /* Configuration */
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#define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */
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#define GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */
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#define GMAC_HASH_LOW 0x0000000c /* Multicast Hash Table Low */
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#define GMAC_MII_ADDR 0x00000010 /* MII Address */
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#define GMAC_MII_DATA 0x00000014 /* MII Data */
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#define GMAC_FLOW_CTRL 0x00000018 /* Flow Control */
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#define GMAC_VLAN_TAG 0x0000001c /* VLAN Tag */
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#define GMAC_VERSION 0x00000020 /* GMAC CORE Version */
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#define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
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#define GMAC_INT_STATUS 0x00000038 /* interrupt status register */
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enum dwmac1000_irq_status {
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lpiis_irq = 0x400,
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time_stamp_irq = 0x0200,
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mmc_rx_csum_offload_irq = 0x0080,
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mmc_tx_irq = 0x0040,
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mmc_rx_irq = 0x0020,
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mmc_irq = 0x0010,
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pmt_irq = 0x0008,
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pcs_ane_irq = 0x0004,
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pcs_link_irq = 0x0002,
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rgmii_irq = 0x0001,
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};
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#define GMAC_INT_MASK 0x0000003c /* interrupt mask register */
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/* PMT Control and Status */
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#define GMAC_PMT 0x0000002c
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enum power_event {
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pointer_reset = 0x80000000,
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global_unicast = 0x00000200,
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wake_up_rx_frame = 0x00000040,
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magic_frame = 0x00000020,
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wake_up_frame_en = 0x00000004,
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magic_pkt_en = 0x00000002,
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power_down = 0x00000001,
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};
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/* Energy Efficient Ethernet (EEE)
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*
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* LPI status, timer and control register offset
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*/
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#define LPI_CTRL_STATUS 0x0030
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#define LPI_TIMER_CTRL 0x0034
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/* LPI control and status defines */
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#define LPI_CTRL_STATUS_LPITXA 0x00080000 /* Enable LPI TX Automate */
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#define LPI_CTRL_STATUS_PLSEN 0x00040000 /* Enable PHY Link Status */
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#define LPI_CTRL_STATUS_PLS 0x00020000 /* PHY Link Status */
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#define LPI_CTRL_STATUS_LPIEN 0x00010000 /* LPI Enable */
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#define LPI_CTRL_STATUS_RLPIST 0x00000200 /* Receive LPI state */
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#define LPI_CTRL_STATUS_TLPIST 0x00000100 /* Transmit LPI state */
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#define LPI_CTRL_STATUS_RLPIEX 0x00000008 /* Receive LPI Exit */
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#define LPI_CTRL_STATUS_RLPIEN 0x00000004 /* Receive LPI Entry */
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#define LPI_CTRL_STATUS_TLPIEX 0x00000002 /* Transmit LPI Exit */
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#define LPI_CTRL_STATUS_TLPIEN 0x00000001 /* Transmit LPI Entry */
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/* GMAC HW ADDR regs */
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#define GMAC_ADDR_HIGH(reg) (((reg > 15) ? 0x00000800 : 0x00000040) + \
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(reg * 8))
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#define GMAC_ADDR_LOW(reg) (((reg > 15) ? 0x00000804 : 0x00000044) + \
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(reg * 8))
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#define GMAC_MAX_PERFECT_ADDRESSES 1
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/* PCS registers (AN/TBI/SGMII/RGMII) offset */
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#define GMAC_AN_CTRL 0x000000c0 /* AN control */
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#define GMAC_AN_STATUS 0x000000c4 /* AN status */
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#define GMAC_ANE_ADV 0x000000c8 /* Auto-Neg. Advertisement */
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#define GMAC_ANE_LPA 0x000000cc /* Auto-Neg. link partener ability */
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#define GMAC_ANE_EXP 0x000000d0 /* ANE expansion */
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#define GMAC_TBI 0x000000d4 /* TBI extend status */
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#define GMAC_S_R_GMII 0x000000d8 /* SGMII RGMII status */
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/* AN Configuration defines */
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#define GMAC_AN_CTRL_RAN 0x00000200 /* Restart Auto-Negotiation */
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#define GMAC_AN_CTRL_ANE 0x00001000 /* Auto-Negotiation Enable */
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#define GMAC_AN_CTRL_ELE 0x00004000 /* External Loopback Enable */
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#define GMAC_AN_CTRL_ECD 0x00010000 /* Enable Comma Detect */
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#define GMAC_AN_CTRL_LR 0x00020000 /* Lock to Reference */
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#define GMAC_AN_CTRL_SGMRAL 0x00040000 /* SGMII RAL Control */
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/* AN Status defines */
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#define GMAC_AN_STATUS_LS 0x00000004 /* Link Status 0:down 1:up */
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#define GMAC_AN_STATUS_ANA 0x00000008 /* Auto-Negotiation Ability */
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#define GMAC_AN_STATUS_ANC 0x00000020 /* Auto-Negotiation Complete */
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#define GMAC_AN_STATUS_ES 0x00000100 /* Extended Status */
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/* Register 54 (SGMII/RGMII status register) */
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#define GMAC_S_R_GMII_LINK 0x8
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#define GMAC_S_R_GMII_SPEED 0x5
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#define GMAC_S_R_GMII_SPEED_SHIFT 0x1
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#define GMAC_S_R_GMII_MODE 0x1
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#define GMAC_S_R_GMII_SPEED_125 2
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#define GMAC_S_R_GMII_SPEED_25 1
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/* Common ADV and LPA defines */
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#define GMAC_ANE_FD (1 << 5)
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#define GMAC_ANE_HD (1 << 6)
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#define GMAC_ANE_PSE (3 << 7)
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#define GMAC_ANE_PSE_SHIFT 7
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/* GMAC Configuration defines */
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#define GMAC_CONTROL_2K 0x08000000 /* IEEE 802.3as 2K packets */
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#define GMAC_CONTROL_TC 0x01000000 /* Transmit Conf. in RGMII/SGMII */
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#define GMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on receive */
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#define GMAC_CONTROL_JD 0x00400000 /* Jabber disable */
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#define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */
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#define GMAC_CONTROL_JE 0x00100000 /* Jumbo frame */
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enum inter_frame_gap {
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GMAC_CONTROL_IFG_88 = 0x00040000,
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GMAC_CONTROL_IFG_80 = 0x00020000,
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GMAC_CONTROL_IFG_40 = 0x000e0000,
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};
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#define GMAC_CONTROL_DCRS 0x00010000 /* Disable carrier sense */
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#define GMAC_CONTROL_PS 0x00008000 /* Port Select 0:GMI 1:MII */
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#define GMAC_CONTROL_FES 0x00004000 /* Speed 0:10 1:100 */
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#define GMAC_CONTROL_DO 0x00002000 /* Disable Rx Own */
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#define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
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#define GMAC_CONTROL_DM 0x00000800 /* Duplex Mode */
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#define GMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */
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#define GMAC_CONTROL_DR 0x00000200 /* Disable Retry */
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#define GMAC_CONTROL_LUD 0x00000100 /* Link up/down */
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#define GMAC_CONTROL_ACS 0x00000080 /* Auto Pad/FCS Stripping */
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#define GMAC_CONTROL_DC 0x00000010 /* Deferral Check */
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#define GMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */
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#define GMAC_CONTROL_RE 0x00000004 /* Receiver Enable */
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#define GMAC_CORE_INIT (GMAC_CONTROL_JD | GMAC_CONTROL_PS | GMAC_CONTROL_ACS | \
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GMAC_CONTROL_BE)
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/* GMAC Frame Filter defines */
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#define GMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */
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#define GMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */
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#define GMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */
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#define GMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */
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#define GMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */
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#define GMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */
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#define GMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */
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#define GMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */
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#define GMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */
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#define GMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */
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/* GMII ADDR defines */
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#define GMAC_MII_ADDR_WRITE 0x00000002 /* MII Write */
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#define GMAC_MII_ADDR_BUSY 0x00000001 /* MII Busy */
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/* GMAC FLOW CTRL defines */
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#define GMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */
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#define GMAC_FLOW_CTRL_PT_SHIFT 16
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#define GMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */
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#define GMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */
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#define GMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */
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/*--- DMA BLOCK defines ---*/
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/* DMA Bus Mode register defines */
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#define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */
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#define DMA_BUS_MODE_DA 0x00000002 /* Arbitration scheme */
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#define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */
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#define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */
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/* Programmable burst length (passed thorugh platform)*/
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#define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */
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#define DMA_BUS_MODE_PBL_SHIFT 8
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#define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */
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enum rx_tx_priority_ratio {
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double_ratio = 0x00004000, /* 2:1 */
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triple_ratio = 0x00008000, /* 3:1 */
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quadruple_ratio = 0x0000c000, /* 4:1 */
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};
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#define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */
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#define DMA_BUS_MODE_MB 0x04000000 /* Mixed burst */
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#define DMA_BUS_MODE_RPBL_MASK 0x003e0000 /* Rx-Programmable Burst Len */
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#define DMA_BUS_MODE_RPBL_SHIFT 17
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#define DMA_BUS_MODE_USP 0x00800000
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#define DMA_BUS_MODE_PBL 0x01000000
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#define DMA_BUS_MODE_AAL 0x02000000
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/* DMA CRS Control and Status Register Mapping */
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#define DMA_HOST_TX_DESC 0x00001048 /* Current Host Tx descriptor */
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#define DMA_HOST_RX_DESC 0x0000104c /* Current Host Rx descriptor */
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/* DMA Bus Mode register defines */
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#define DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */
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#define DMA_BUS_PR_RATIO_SHIFT 14
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#define DMA_BUS_FB 0x00010000 /* Fixed Burst */
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/* DMA operation mode defines (start/stop tx/rx are placed in common header)*/
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/* Disable Drop TCP/IP csum error */
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#define DMA_CONTROL_DT 0x04000000
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#define DMA_CONTROL_RSF 0x02000000 /* Receive Store and Forward */
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#define DMA_CONTROL_DFF 0x01000000 /* Disaable flushing */
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/* Threshold for Activating the FC */
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enum rfa {
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act_full_minus_1 = 0x00800000,
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act_full_minus_2 = 0x00800200,
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act_full_minus_3 = 0x00800400,
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act_full_minus_4 = 0x00800600,
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};
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/* Threshold for Deactivating the FC */
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enum rfd {
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deac_full_minus_1 = 0x00400000,
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deac_full_minus_2 = 0x00400800,
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deac_full_minus_3 = 0x00401000,
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deac_full_minus_4 = 0x00401800,
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};
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#define DMA_CONTROL_TSF 0x00200000 /* Transmit Store and Forward */
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enum ttc_control {
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DMA_CONTROL_TTC_64 = 0x00000000,
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DMA_CONTROL_TTC_128 = 0x00004000,
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DMA_CONTROL_TTC_192 = 0x00008000,
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DMA_CONTROL_TTC_256 = 0x0000c000,
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DMA_CONTROL_TTC_40 = 0x00010000,
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DMA_CONTROL_TTC_32 = 0x00014000,
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DMA_CONTROL_TTC_24 = 0x00018000,
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DMA_CONTROL_TTC_16 = 0x0001c000,
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};
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#define DMA_CONTROL_TC_TX_MASK 0xfffe3fff
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#define DMA_CONTROL_EFC 0x00000100
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#define DMA_CONTROL_FEF 0x00000080
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#define DMA_CONTROL_FUF 0x00000040
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enum rtc_control {
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DMA_CONTROL_RTC_64 = 0x00000000,
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DMA_CONTROL_RTC_32 = 0x00000008,
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DMA_CONTROL_RTC_96 = 0x00000010,
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DMA_CONTROL_RTC_128 = 0x00000018,
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};
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#define DMA_CONTROL_TC_RX_MASK 0xffffffe7
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#define DMA_CONTROL_OSF 0x00000004 /* Operate on second frame */
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/* MMC registers offset */
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#define GMAC_MMC_CTRL 0x100
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#define GMAC_MMC_RX_INTR 0x104
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#define GMAC_MMC_TX_INTR 0x108
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#define GMAC_MMC_RX_CSUM_OFFLOAD 0x208
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#define GMAC_EXTHASH_BASE 0x500
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extern const struct stmmac_dma_ops dwmac1000_dma_ops;
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#endif /* __DWMAC1000_H__ */
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