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https://github.com/edk2-porting/linux-next.git
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322aafa664
* 'x86-mrst-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (30 commits)
x86, mrst: Fix whitespace breakage in apb_timer.c
x86, mrst: Fix APB timer per cpu clockevent
x86, mrst: Remove X86_MRST dependency on PCI_IOAPIC
x86, olpc: Use pci subarch init for OLPC
x86, pci: Add arch_init to x86_init abstraction
x86, mrst: Add Kconfig dependencies for Moorestown
x86, pci: Exclude Moorestown PCI code if CONFIG_X86_MRST=n
x86, numaq: Make CONFIG_X86_NUMAQ depend on CONFIG_PCI
x86, pci: Add sanity check for PCI fixed bar probing
x86, legacy_irq: Remove duplicate vector assigment
x86, legacy_irq: Remove left over nr_legacy_irqs
x86, mrst: Platform clock setup code
x86, apbt: Moorestown APB system timer driver
x86, mrst: Add vrtc platform data setup code
x86, mrst: Add platform timer info parsing code
x86, mrst: Fill in PCI functions in x86_init layer
x86, mrst: Add dummy legacy pic to platform setup
x86/PCI: Moorestown PCI support
x86, ioapic: Add dummy ioapic functions
x86, ioapic: Early enable ioapic for timer irq
...
Fixed up semantic conflict of new clocksources due to commit
17622339af ("clocksource: add argument to resume callback").
177 lines
6.2 KiB
C
177 lines
6.2 KiB
C
/*
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* Written by: Patricia Gaughen, IBM Corporation
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*
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* Copyright (C) 2002, IBM Corp.
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*
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Send feedback to <gone@us.ibm.com>
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*/
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#ifndef _ASM_X86_NUMAQ_H
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#define _ASM_X86_NUMAQ_H
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#ifdef CONFIG_X86_NUMAQ
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extern int found_numaq;
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extern int get_memcfg_numaq(void);
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extern int pci_numaq_init(void);
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extern void *xquad_portio;
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#define XQUAD_PORTIO_BASE 0xfe400000
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#define XQUAD_PORTIO_QUAD 0x40000 /* 256k per quad. */
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#define XQUAD_PORT_ADDR(port, quad) (xquad_portio + (XQUAD_PORTIO_QUAD*quad) + port)
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/*
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* SYS_CFG_DATA_PRIV_ADDR, struct eachquadmem, and struct sys_cfg_data are the
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*/
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#define SYS_CFG_DATA_PRIV_ADDR 0x0009d000 /* place for scd in private
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quad space */
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/*
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* Communication area for each processor on lynxer-processor tests.
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*
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* NOTE: If you change the size of this eachproc structure you need
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* to change the definition for EACH_QUAD_SIZE.
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*/
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struct eachquadmem {
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unsigned int priv_mem_start; /* Starting address of this */
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/* quad's private memory. */
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/* This is always 0. */
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/* In MB. */
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unsigned int priv_mem_size; /* Size of this quad's */
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/* private memory. */
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/* In MB. */
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unsigned int low_shrd_mem_strp_start;/* Starting address of this */
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/* quad's low shared block */
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/* (untranslated). */
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/* In MB. */
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unsigned int low_shrd_mem_start; /* Starting address of this */
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/* quad's low shared memory */
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/* (untranslated). */
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/* In MB. */
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unsigned int low_shrd_mem_size; /* Size of this quad's low */
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/* shared memory. */
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/* In MB. */
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unsigned int lmmio_copb_start; /* Starting address of this */
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/* quad's local memory */
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/* mapped I/O in the */
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/* compatibility OPB. */
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/* In MB. */
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unsigned int lmmio_copb_size; /* Size of this quad's local */
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/* memory mapped I/O in the */
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/* compatibility OPB. */
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/* In MB. */
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unsigned int lmmio_nopb_start; /* Starting address of this */
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/* quad's local memory */
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/* mapped I/O in the */
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/* non-compatibility OPB. */
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/* In MB. */
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unsigned int lmmio_nopb_size; /* Size of this quad's local */
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/* memory mapped I/O in the */
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/* non-compatibility OPB. */
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/* In MB. */
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unsigned int io_apic_0_start; /* Starting address of I/O */
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/* APIC 0. */
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unsigned int io_apic_0_sz; /* Size I/O APIC 0. */
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unsigned int io_apic_1_start; /* Starting address of I/O */
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/* APIC 1. */
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unsigned int io_apic_1_sz; /* Size I/O APIC 1. */
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unsigned int hi_shrd_mem_start; /* Starting address of this */
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/* quad's high shared memory.*/
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/* In MB. */
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unsigned int hi_shrd_mem_size; /* Size of this quad's high */
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/* shared memory. */
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/* In MB. */
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unsigned int mps_table_addr; /* Address of this quad's */
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/* MPS tables from BIOS, */
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/* in system space.*/
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unsigned int lcl_MDC_pio_addr; /* Port-I/O address for */
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/* local access of MDC. */
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unsigned int rmt_MDC_mmpio_addr; /* MM-Port-I/O address for */
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/* remote access of MDC. */
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unsigned int mm_port_io_start; /* Starting address of this */
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/* quad's memory mapped Port */
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/* I/O space. */
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unsigned int mm_port_io_size; /* Size of this quad's memory*/
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/* mapped Port I/O space. */
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unsigned int mm_rmt_io_apic_start; /* Starting address of this */
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/* quad's memory mapped */
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/* remote I/O APIC space. */
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unsigned int mm_rmt_io_apic_size; /* Size of this quad's memory*/
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/* mapped remote I/O APIC */
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/* space. */
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unsigned int mm_isa_start; /* Starting address of this */
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/* quad's memory mapped ISA */
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/* space (contains MDC */
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/* memory space). */
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unsigned int mm_isa_size; /* Size of this quad's memory*/
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/* mapped ISA space (contains*/
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/* MDC memory space). */
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unsigned int rmt_qmi_addr; /* Remote addr to access QMI.*/
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unsigned int lcl_qmi_addr; /* Local addr to access QMI. */
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};
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/*
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* Note: This structure must be NOT be changed unless the multiproc and
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* OS are changed to reflect the new structure.
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*/
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struct sys_cfg_data {
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unsigned int quad_id;
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unsigned int bsp_proc_id; /* Boot Strap Processor in this quad. */
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unsigned int scd_version; /* Version number of this table. */
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unsigned int first_quad_id;
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unsigned int quads_present31_0; /* 1 bit for each quad */
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unsigned int quads_present63_32; /* 1 bit for each quad */
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unsigned int config_flags;
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unsigned int boot_flags;
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unsigned int csr_start_addr; /* Absolute value (not in MB) */
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unsigned int csr_size; /* Absolute value (not in MB) */
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unsigned int lcl_apic_start_addr; /* Absolute value (not in MB) */
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unsigned int lcl_apic_size; /* Absolute value (not in MB) */
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unsigned int low_shrd_mem_base; /* 0 or 512MB or 1GB */
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unsigned int low_shrd_mem_quad_offset; /* 0,128M,256M,512M,1G */
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/* may not be totally populated */
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unsigned int split_mem_enbl; /* 0 for no low shared memory */
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unsigned int mmio_sz; /* Size of total system memory mapped I/O */
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/* (in MB). */
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unsigned int quad_spin_lock; /* Spare location used for quad */
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/* bringup. */
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unsigned int nonzero55; /* For checksumming. */
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unsigned int nonzeroaa; /* For checksumming. */
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unsigned int scd_magic_number;
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unsigned int system_type;
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unsigned int checksum;
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/*
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* memory configuration area for each quad
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*/
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struct eachquadmem eq[MAX_NUMNODES]; /* indexed by quad id */
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};
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void numaq_tsc_disable(void);
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#else
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static inline int get_memcfg_numaq(void)
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{
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return 0;
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}
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#endif /* CONFIG_X86_NUMAQ */
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#endif /* _ASM_X86_NUMAQ_H */
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