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03daa99ef5
Add compatible "fsl,mpic-msi-v4.3" for MPIC v4.3. MPIC v4.3 contains MSIIR and MSIIR1. MSIIR supports 8 MSI registers and MSIIR1 supports 16 MSI registers, but uses different IBS and SRS shift. When using MSIR1, the interrupt number is not consecutive. It is hard to use 'msi-available-ranges' to describe the ranges of the available interrupt, so MPIC v4.3 does not support this property. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> [scottwood@freescale.com: minor grammar fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
117 lines
4.6 KiB
Plaintext
117 lines
4.6 KiB
Plaintext
* Freescale MSI interrupt controller
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Required properties:
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- compatible : compatible list, may contain one or two entries
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The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
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etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
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"fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
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version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
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provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
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should be used. The first entry is optional; the second entry is
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required.
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- reg : It may contain one or two regions. The first region should contain
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the address and the length of the shared message interrupt register set.
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The second region should contain the address of aliased MSIIR or MSIIR1
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register for platforms that have such an alias, if using MSIIR1, the second
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region must be added because different MSI group has different MSIIR1 offset.
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- interrupts : each one of the interrupts here is one entry per 32 MSIs,
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and routed to the host interrupt controller. the interrupts should
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be set as edge sensitive. If msi-available-ranges is present, only
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the interrupts that correspond to available ranges shall be present.
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- interrupt-parent: the phandle for the interrupt controller
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that services interrupts for this device. for 83xx cpu, the interrupts
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are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
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to MPIC.
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Optional properties:
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- msi-available-ranges: use <start count> style section to define which
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msi interrupt can be used in the 256 msi interrupts. This property is
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optional, without this, all the MSI interrupts can be used.
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Each available range must begin and end on a multiple of 32 (i.e.
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no splitting an individual MSI register or the associated PIC interrupt).
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MPIC v4.3 does not support this property because the 32 interrupts of an
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individual register are not continuous when using MSIIR1.
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- msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register
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is used for MSI messaging. The address of MSIIR in PCI address space is
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the MSI message address.
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This property may be used in virtualized environments where the hypervisor
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has created an alternate mapping for the MSIR block. See below for an
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explanation.
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Example:
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msi@41600 {
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compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
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reg = <0x41600 0x80>;
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msi-available-ranges = <0 0x100>;
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interrupts = <
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0xe0 0
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0xe1 0
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0xe2 0
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0xe3 0
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0xe4 0
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0xe5 0
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0xe6 0
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0xe7 0>;
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interrupt-parent = <&mpic>;
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};
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msi@41600 {
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compatible = "fsl,mpic-msi-v4.3";
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reg = <0x41600 0x200 0x44148 4>;
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interrupts = <
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0xe0 0 0 0
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0xe1 0 0 0
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0xe2 0 0 0
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0xe3 0 0 0
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0xe4 0 0 0
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0xe5 0 0 0
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0xe6 0 0 0
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0xe7 0 0 0
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0x100 0 0 0
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0x101 0 0 0
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0x102 0 0 0
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0x103 0 0 0
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0x104 0 0 0
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0x105 0 0 0
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0x106 0 0 0
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0x107 0 0 0>;
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};
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The Freescale hypervisor and msi-address-64
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-------------------------------------------
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Normally, PCI devices have access to all of CCSR via an ATMU mapping. The
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Freescale MSI driver calculates the address of MSIIR (in the MSI register
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block) and sets that address as the MSI message address.
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In a virtualized environment, the hypervisor may need to create an IOMMU
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mapping for MSIIR. The Freescale ePAPR hypervisor has this requirement
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because of hardware limitations of the Peripheral Access Management Unit
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(PAMU), which is currently the only IOMMU that the hypervisor supports.
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The ATMU is programmed with the guest physical address, and the PAMU
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intercepts transactions and reroutes them to the true physical address.
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In the PAMU, each PCI controller is given only one primary window. The
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PAMU restricts DMA operations so that they can only occur within a window.
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Because PCI devices must be able to DMA to memory, the primary window must
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be used to cover all of the guest's memory space.
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PAMU primary windows can be divided into 256 subwindows, and each
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subwindow can have its own address mapping ("guest physical" to "true
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physical"). However, each subwindow has to have the same alignment, which
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means they cannot be located at just any address. Because of these
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restrictions, it is usually impossible to create a 4KB subwindow that
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covers MSIIR where it's normally located.
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Therefore, the hypervisor has to create a subwindow inside the same
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primary window used for memory, but mapped to the MSIR block (where MSIIR
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lives). The first subwindow after the end of guest memory is used for
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this. The address specified in the msi-address-64 property is the PCI
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address of MSIIR. The hypervisor configures the PAMU to map that address to
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the true physical address of MSIIR.
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