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The CoreNet coherency fabric is a fabric-oriented, conectivity infrastructure that enables the implementation of coherent, multicore systems. The CCF acts as a central interconnect for cores, platform-level caches, memory subsystem, peripheral devices and I/O host bridges in the system. Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com> [scottwood@freescale.com: formatting and minor changes] Signed-off-by: Scott Wood <scottwood@freescale.com>
47 lines
1.4 KiB
Plaintext
47 lines
1.4 KiB
Plaintext
Freescale CoreNet Coherency Fabric(CCF) Device Tree Binding
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DESCRIPTION
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The CoreNet coherency fabric is a fabric-oriented, connectivity infrastructure
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that enables the implementation of coherent, multicore systems.
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Required properties:
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- compatible: <string list>
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fsl,corenet1-cf - CoreNet coherency fabric version 1.
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Example chips: T4240, B4860
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fsl,corenet2-cf - CoreNet coherency fabric version 2.
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Example chips: P5040, P5020, P4080, P3041, P2041
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fsl,corenet-cf - Used to represent the common registers
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between CCF version 1 and CCF version 2. This compatible
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is retained for compatibility reasons, as it was already
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used for both CCF version 1 chips and CCF version 2
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chips. It should be specified after either
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"fsl,corenet1-cf" or "fsl,corenet2-cf".
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- reg: <prop-encoded-array>
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A standard property. Represents the CCF registers.
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- interrupts: <prop-encoded-array>
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Interrupt mapping for CCF error interrupt.
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- fsl,ccf-num-csdids: <u32>
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Specifies the number of Coherency Subdomain ID Port Mapping
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Registers that are supported by the CCF.
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- fsl,ccf-num-snoopids: <u32>
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Specifies the number of Snoop ID Port Mapping Registers that
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are supported by CCF.
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Example:
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corenet-cf@18000 {
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compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
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reg = <0x18000 0x1000>;
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interrupts = <16 2 1 31>;
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fsl,ccf-num-csdids = <32>;
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fsl,ccf-num-snoopids = <32>;
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};
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