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573a652fb0
Support for the Tauros2 L2 cache controller as used with the PJ1 and PJ4 CPUs. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com> |
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.. | ||
include/mach | ||
addr-map.c | ||
common.c | ||
common.h | ||
dove-db-setup.c | ||
irq.c | ||
Kconfig | ||
Makefile | ||
Makefile.boot | ||
pcie.c |