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0523b8f414
pcr_dbg is a wrapper of dev_dbg, which can save some code, and help to enable/disable debug message static. Signed-off-by: Micky Ching <micky_ching@realsil.com.cn> Signed-off-by: Lee Jones <lee.jones@linaro.org>
509 lines
14 KiB
C
509 lines
14 KiB
C
/* Driver for Realtek PCI-Express card reader
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*
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* Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2, or (at your option) any
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* later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* Author:
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* Wei WANG <wei_wang@realsil.com.cn>
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* Roger Tseng <rogerable@realtek.com>
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*/
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#include <linux/module.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/mfd/rtsx_pci.h>
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#include "rtsx_pcr.h"
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static u8 rtl8411_get_ic_version(struct rtsx_pcr *pcr)
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{
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u8 val;
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rtsx_pci_read_register(pcr, SYS_VER, &val);
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return val & 0x0F;
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}
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static int rtl8411b_is_qfn48(struct rtsx_pcr *pcr)
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{
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u8 val = 0;
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rtsx_pci_read_register(pcr, RTL8411B_PACKAGE_MODE, &val);
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if (val & 0x2)
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return 1;
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else
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return 0;
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}
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static void rtl8411_fetch_vendor_settings(struct rtsx_pcr *pcr)
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{
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u32 reg1 = 0;
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u8 reg3 = 0;
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rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®1);
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pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg1);
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if (!rtsx_vendor_setting_valid(reg1))
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return;
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pcr->aspm_en = rtsx_reg_to_aspm(reg1);
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pcr->sd30_drive_sel_1v8 =
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map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg1));
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pcr->card_drive_sel &= 0x3F;
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pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg1);
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rtsx_pci_read_config_byte(pcr, PCR_SETTING_REG3, ®3);
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pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG3, reg3);
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pcr->sd30_drive_sel_3v3 = rtl8411_reg_to_sd30_drive_sel_3v3(reg3);
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}
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static void rtl8411b_fetch_vendor_settings(struct rtsx_pcr *pcr)
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{
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u32 reg = 0;
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rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®);
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pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
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if (!rtsx_vendor_setting_valid(reg))
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return;
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pcr->aspm_en = rtsx_reg_to_aspm(reg);
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pcr->sd30_drive_sel_1v8 =
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map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg));
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pcr->sd30_drive_sel_3v3 =
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map_sd_drive(rtl8411b_reg_to_sd30_drive_sel_3v3(reg));
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}
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static void rtl8411_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
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{
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rtsx_pci_write_register(pcr, FPDCTL, 0x07, 0x07);
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}
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static int rtl8411_extra_init_hw(struct rtsx_pcr *pcr)
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{
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rtsx_pci_init_cmd(pcr);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
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0xFF, pcr->sd30_drive_sel_3v3);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CD_PAD_CTL,
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CD_DISABLE_MASK | CD_AUTO_DISABLE, CD_ENABLE);
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return rtsx_pci_send_cmd(pcr, 100);
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}
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static int rtl8411b_extra_init_hw(struct rtsx_pcr *pcr)
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{
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rtsx_pci_init_cmd(pcr);
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if (rtl8411b_is_qfn48(pcr))
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
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CARD_PULL_CTL3, 0xFF, 0xF5);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
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0xFF, pcr->sd30_drive_sel_3v3);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CD_PAD_CTL,
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CD_DISABLE_MASK | CD_AUTO_DISABLE, CD_ENABLE);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, FUNC_FORCE_CTL,
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0x06, 0x00);
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return rtsx_pci_send_cmd(pcr, 100);
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}
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static int rtl8411_turn_on_led(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x00);
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}
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static int rtl8411_turn_off_led(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x01);
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}
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static int rtl8411_enable_auto_blink(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0xFF, 0x0D);
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}
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static int rtl8411_disable_auto_blink(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0x08, 0x00);
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}
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static int rtl8411_card_power_on(struct rtsx_pcr *pcr, int card)
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{
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int err;
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rtsx_pci_init_cmd(pcr);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
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BPP_POWER_MASK, BPP_POWER_5_PERCENT_ON);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_CTL,
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BPP_LDO_POWB, BPP_LDO_SUSPEND);
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err = rtsx_pci_send_cmd(pcr, 100);
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if (err < 0)
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return err;
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/* To avoid too large in-rush current */
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udelay(150);
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err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
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BPP_POWER_MASK, BPP_POWER_10_PERCENT_ON);
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if (err < 0)
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return err;
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udelay(150);
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err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
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BPP_POWER_MASK, BPP_POWER_15_PERCENT_ON);
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if (err < 0)
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return err;
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udelay(150);
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err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
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BPP_POWER_MASK, BPP_POWER_ON);
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if (err < 0)
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return err;
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return rtsx_pci_write_register(pcr, LDO_CTL, BPP_LDO_POWB, BPP_LDO_ON);
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}
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static int rtl8411_card_power_off(struct rtsx_pcr *pcr, int card)
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{
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int err;
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err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
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BPP_POWER_MASK, BPP_POWER_OFF);
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if (err < 0)
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return err;
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return rtsx_pci_write_register(pcr, LDO_CTL,
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BPP_LDO_POWB, BPP_LDO_SUSPEND);
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}
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static int rtl8411_do_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage,
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int bpp_tuned18_shift, int bpp_asic_1v8)
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{
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u8 mask, val;
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int err;
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mask = (BPP_REG_TUNED18 << bpp_tuned18_shift) | BPP_PAD_MASK;
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if (voltage == OUTPUT_3V3) {
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err = rtsx_pci_write_register(pcr,
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SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_3v3);
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if (err < 0)
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return err;
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val = (BPP_ASIC_3V3 << bpp_tuned18_shift) | BPP_PAD_3V3;
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} else if (voltage == OUTPUT_1V8) {
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err = rtsx_pci_write_register(pcr,
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SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_1v8);
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if (err < 0)
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return err;
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val = (bpp_asic_1v8 << bpp_tuned18_shift) | BPP_PAD_1V8;
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} else {
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return -EINVAL;
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}
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return rtsx_pci_write_register(pcr, LDO_CTL, mask, val);
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}
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static int rtl8411_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
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{
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return rtl8411_do_switch_output_voltage(pcr, voltage,
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BPP_TUNED18_SHIFT_8411, BPP_ASIC_1V8);
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}
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static int rtl8402_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
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{
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return rtl8411_do_switch_output_voltage(pcr, voltage,
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BPP_TUNED18_SHIFT_8402, BPP_ASIC_2V0);
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}
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static unsigned int rtl8411_cd_deglitch(struct rtsx_pcr *pcr)
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{
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unsigned int card_exist;
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card_exist = rtsx_pci_readl(pcr, RTSX_BIPR);
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card_exist &= CARD_EXIST;
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if (!card_exist) {
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/* Enable card CD */
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rtsx_pci_write_register(pcr, CD_PAD_CTL,
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CD_DISABLE_MASK, CD_ENABLE);
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/* Enable card interrupt */
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rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x00);
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return 0;
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}
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if (hweight32(card_exist) > 1) {
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rtsx_pci_write_register(pcr, CARD_PWR_CTL,
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BPP_POWER_MASK, BPP_POWER_5_PERCENT_ON);
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msleep(100);
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card_exist = rtsx_pci_readl(pcr, RTSX_BIPR);
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if (card_exist & MS_EXIST)
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card_exist = MS_EXIST;
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else if (card_exist & SD_EXIST)
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card_exist = SD_EXIST;
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else
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card_exist = 0;
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rtsx_pci_write_register(pcr, CARD_PWR_CTL,
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BPP_POWER_MASK, BPP_POWER_OFF);
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pcr_dbg(pcr, "After CD deglitch, card_exist = 0x%x\n",
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card_exist);
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}
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if (card_exist & MS_EXIST) {
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/* Disable SD interrupt */
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rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x40);
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rtsx_pci_write_register(pcr, CD_PAD_CTL,
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CD_DISABLE_MASK, MS_CD_EN_ONLY);
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} else if (card_exist & SD_EXIST) {
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/* Disable MS interrupt */
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rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x80);
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rtsx_pci_write_register(pcr, CD_PAD_CTL,
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CD_DISABLE_MASK, SD_CD_EN_ONLY);
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}
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return card_exist;
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}
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static int rtl8411_conv_clk_and_div_n(int input, int dir)
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{
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int output;
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if (dir == CLK_TO_DIV_N)
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output = input * 4 / 5 - 2;
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else
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output = (input + 2) * 5 / 4;
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return output;
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}
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static const struct pcr_ops rtl8411_pcr_ops = {
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.fetch_vendor_settings = rtl8411_fetch_vendor_settings,
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.extra_init_hw = rtl8411_extra_init_hw,
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.optimize_phy = NULL,
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.turn_on_led = rtl8411_turn_on_led,
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.turn_off_led = rtl8411_turn_off_led,
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.enable_auto_blink = rtl8411_enable_auto_blink,
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.disable_auto_blink = rtl8411_disable_auto_blink,
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.card_power_on = rtl8411_card_power_on,
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.card_power_off = rtl8411_card_power_off,
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.switch_output_voltage = rtl8411_switch_output_voltage,
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.cd_deglitch = rtl8411_cd_deglitch,
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.conv_clk_and_div_n = rtl8411_conv_clk_and_div_n,
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.force_power_down = rtl8411_force_power_down,
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};
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static const struct pcr_ops rtl8402_pcr_ops = {
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.fetch_vendor_settings = rtl8411_fetch_vendor_settings,
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.extra_init_hw = rtl8411_extra_init_hw,
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.optimize_phy = NULL,
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.turn_on_led = rtl8411_turn_on_led,
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.turn_off_led = rtl8411_turn_off_led,
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.enable_auto_blink = rtl8411_enable_auto_blink,
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.disable_auto_blink = rtl8411_disable_auto_blink,
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.card_power_on = rtl8411_card_power_on,
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.card_power_off = rtl8411_card_power_off,
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.switch_output_voltage = rtl8402_switch_output_voltage,
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.cd_deglitch = rtl8411_cd_deglitch,
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.conv_clk_and_div_n = rtl8411_conv_clk_and_div_n,
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.force_power_down = rtl8411_force_power_down,
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};
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static const struct pcr_ops rtl8411b_pcr_ops = {
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.fetch_vendor_settings = rtl8411b_fetch_vendor_settings,
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.extra_init_hw = rtl8411b_extra_init_hw,
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.optimize_phy = NULL,
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.turn_on_led = rtl8411_turn_on_led,
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.turn_off_led = rtl8411_turn_off_led,
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.enable_auto_blink = rtl8411_enable_auto_blink,
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.disable_auto_blink = rtl8411_disable_auto_blink,
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.card_power_on = rtl8411_card_power_on,
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.card_power_off = rtl8411_card_power_off,
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.switch_output_voltage = rtl8411_switch_output_voltage,
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.cd_deglitch = rtl8411_cd_deglitch,
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.conv_clk_and_div_n = rtl8411_conv_clk_and_div_n,
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.force_power_down = rtl8411_force_power_down,
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};
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/* SD Pull Control Enable:
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* SD_DAT[3:0] ==> pull up
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* SD_CD ==> pull up
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* SD_WP ==> pull up
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* SD_CMD ==> pull up
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* SD_CLK ==> pull down
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*/
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static const u32 rtl8411_sd_pull_ctl_enable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA),
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RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
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RTSX_REG_PAIR(CARD_PULL_CTL3, 0xA9),
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RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09),
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RTSX_REG_PAIR(CARD_PULL_CTL5, 0x09),
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RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
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0,
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};
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/* SD Pull Control Disable:
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* SD_DAT[3:0] ==> pull down
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* SD_CD ==> pull up
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* SD_WP ==> pull down
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* SD_CMD ==> pull down
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* SD_CLK ==> pull down
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*/
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static const u32 rtl8411_sd_pull_ctl_disable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
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RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95),
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RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09),
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RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05),
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RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
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0,
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};
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/* MS Pull Control Enable:
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* MS CD ==> pull up
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* others ==> pull down
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*/
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static const u32 rtl8411_ms_pull_ctl_enable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
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RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95),
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RTSX_REG_PAIR(CARD_PULL_CTL4, 0x05),
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RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05),
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RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
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0,
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};
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/* MS Pull Control Disable:
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* MS CD ==> pull up
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* others ==> pull down
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*/
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static const u32 rtl8411_ms_pull_ctl_disable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
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RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95),
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RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09),
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RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05),
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RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
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0,
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};
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static const u32 rtl8411b_qfn64_sd_pull_ctl_enable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA),
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RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
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RTSX_REG_PAIR(CARD_PULL_CTL3, 0x09 | 0xD0),
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RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50),
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RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50),
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RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
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0,
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};
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static const u32 rtl8411b_qfn48_sd_pull_ctl_enable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
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|
RTSX_REG_PAIR(CARD_PULL_CTL3, 0x69 | 0x90),
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RTSX_REG_PAIR(CARD_PULL_CTL6, 0x08 | 0x11),
|
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0,
|
|
};
|
|
|
|
static const u32 rtl8411b_qfn64_sd_pull_ctl_disable_tbl[] = {
|
|
RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
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|
RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
|
|
0,
|
|
};
|
|
|
|
static const u32 rtl8411b_qfn48_sd_pull_ctl_disable_tbl[] = {
|
|
RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
|
|
0,
|
|
};
|
|
|
|
static const u32 rtl8411b_qfn64_ms_pull_ctl_enable_tbl[] = {
|
|
RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL4, 0x05 | 0x50),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
|
|
0,
|
|
};
|
|
|
|
static const u32 rtl8411b_qfn48_ms_pull_ctl_enable_tbl[] = {
|
|
RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
|
|
0,
|
|
};
|
|
|
|
static const u32 rtl8411b_qfn64_ms_pull_ctl_disable_tbl[] = {
|
|
RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
|
|
0,
|
|
};
|
|
|
|
static const u32 rtl8411b_qfn48_ms_pull_ctl_disable_tbl[] = {
|
|
RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
|
|
0,
|
|
};
|
|
|
|
static void rtl8411_init_common_params(struct rtsx_pcr *pcr)
|
|
{
|
|
pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
|
|
pcr->num_slots = 2;
|
|
pcr->flags = 0;
|
|
pcr->card_drive_sel = RTL8411_CARD_DRIVE_DEFAULT;
|
|
pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B;
|
|
pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D;
|
|
pcr->aspm_en = ASPM_L1_EN;
|
|
pcr->tx_initial_phase = SET_CLOCK_PHASE(23, 7, 14);
|
|
pcr->rx_initial_phase = SET_CLOCK_PHASE(4, 3, 10);
|
|
pcr->ic_version = rtl8411_get_ic_version(pcr);
|
|
}
|
|
|
|
void rtl8411_init_params(struct rtsx_pcr *pcr)
|
|
{
|
|
rtl8411_init_common_params(pcr);
|
|
pcr->ops = &rtl8411_pcr_ops;
|
|
set_pull_ctrl_tables(pcr, rtl8411);
|
|
}
|
|
|
|
void rtl8411b_init_params(struct rtsx_pcr *pcr)
|
|
{
|
|
rtl8411_init_common_params(pcr);
|
|
pcr->ops = &rtl8411b_pcr_ops;
|
|
if (rtl8411b_is_qfn48(pcr))
|
|
set_pull_ctrl_tables(pcr, rtl8411b_qfn48);
|
|
else
|
|
set_pull_ctrl_tables(pcr, rtl8411b_qfn64);
|
|
}
|
|
|
|
void rtl8402_init_params(struct rtsx_pcr *pcr)
|
|
{
|
|
rtl8411_init_common_params(pcr);
|
|
pcr->ops = &rtl8402_pcr_ops;
|
|
set_pull_ctrl_tables(pcr, rtl8411);
|
|
}
|