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81ec988981
The C6X SoCs contain several PLL controllers each with up to 16 clock outputs feeding into the cores or peripheral clock domains. The hardware is very similar to arm/mach-davinci clocks. This is still a work in progress which needs to be updated once device tree clock binding changes shake out. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
149 lines
3.5 KiB
C
149 lines
3.5 KiB
C
/*
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* TI C64X clock definitions
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*
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* Copyright (C) 2010, 2011 Texas Instruments.
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* Contributed by: Mark Salter <msalter@redhat.com>
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*
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* Copied heavily from arm/mach-davinci/clock.h, so:
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*
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* Copyright (C) 2006-2007 Texas Instruments.
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* Copyright (C) 2008-2009 Deep Root Systems, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASM_C6X_CLOCK_H
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#define _ASM_C6X_CLOCK_H
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#ifndef __ASSEMBLER__
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#include <linux/list.h>
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/* PLL/Reset register offsets */
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#define PLLCTL 0x100
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#define PLLM 0x110
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#define PLLPRE 0x114
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#define PLLDIV1 0x118
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#define PLLDIV2 0x11c
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#define PLLDIV3 0x120
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#define PLLPOST 0x128
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#define PLLCMD 0x138
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#define PLLSTAT 0x13c
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#define PLLALNCTL 0x140
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#define PLLDCHANGE 0x144
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#define PLLCKEN 0x148
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#define PLLCKSTAT 0x14c
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#define PLLSYSTAT 0x150
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#define PLLDIV4 0x160
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#define PLLDIV5 0x164
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#define PLLDIV6 0x168
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#define PLLDIV7 0x16c
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#define PLLDIV8 0x170
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#define PLLDIV9 0x174
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#define PLLDIV10 0x178
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#define PLLDIV11 0x17c
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#define PLLDIV12 0x180
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#define PLLDIV13 0x184
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#define PLLDIV14 0x188
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#define PLLDIV15 0x18c
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#define PLLDIV16 0x190
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/* PLLM register bits */
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#define PLLM_PLLM_MASK 0xff
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#define PLLM_VAL(x) ((x) - 1)
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/* PREDIV register bits */
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#define PLLPREDIV_EN BIT(15)
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#define PLLPREDIV_VAL(x) ((x) - 1)
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/* PLLCTL register bits */
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#define PLLCTL_PLLEN BIT(0)
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#define PLLCTL_PLLPWRDN BIT(1)
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#define PLLCTL_PLLRST BIT(3)
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#define PLLCTL_PLLDIS BIT(4)
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#define PLLCTL_PLLENSRC BIT(5)
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#define PLLCTL_CLKMODE BIT(8)
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/* PLLCMD register bits */
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#define PLLCMD_GOSTAT BIT(0)
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/* PLLSTAT register bits */
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#define PLLSTAT_GOSTAT BIT(0)
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/* PLLDIV register bits */
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#define PLLDIV_EN BIT(15)
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#define PLLDIV_RATIO_MASK 0x1f
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#define PLLDIV_RATIO(x) ((x) - 1)
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struct pll_data;
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struct clk {
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struct list_head node;
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struct module *owner;
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const char *name;
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unsigned long rate;
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int usecount;
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u32 flags;
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struct clk *parent;
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struct list_head children; /* list of children */
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struct list_head childnode; /* parent's child list node */
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struct pll_data *pll_data;
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u32 div;
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unsigned long (*recalc) (struct clk *);
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int (*set_rate) (struct clk *clk, unsigned long rate);
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int (*round_rate) (struct clk *clk, unsigned long rate);
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};
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/* Clock flags: SoC-specific flags start at BIT(16) */
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#define ALWAYS_ENABLED BIT(1)
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#define CLK_PLL BIT(2) /* PLL-derived clock */
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#define PRE_PLL BIT(3) /* source is before PLL mult/div */
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#define FIXED_DIV_PLL BIT(4) /* fixed divisor from PLL */
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#define FIXED_RATE_PLL BIT(5) /* fixed ouput rate PLL */
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#define MAX_PLL_SYSCLKS 16
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struct pll_data {
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void __iomem *base;
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u32 num;
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u32 flags;
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u32 input_rate;
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u32 bypass_delay; /* in loops */
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u32 reset_delay; /* in loops */
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u32 lock_delay; /* in loops */
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struct clk sysclks[MAX_PLL_SYSCLKS + 1];
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};
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/* pll_data flag bit */
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#define PLL_HAS_PRE BIT(0)
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#define PLL_HAS_MUL BIT(1)
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#define PLL_HAS_POST BIT(2)
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#define CLK(dev, con, ck) \
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{ \
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.dev_id = dev, \
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.con_id = con, \
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.clk = ck, \
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} \
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extern void c6x_clks_init(struct clk_lookup *clocks);
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extern int clk_register(struct clk *clk);
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extern void clk_unregister(struct clk *clk);
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extern void c64x_setup_clocks(void);
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extern struct pll_data c6x_soc_pll1;
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extern struct clk clkin1;
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extern struct clk c6x_core_clk;
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extern struct clk c6x_i2c_clk;
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extern struct clk c6x_watchdog_clk;
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extern struct clk c6x_mcbsp1_clk;
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extern struct clk c6x_mcbsp2_clk;
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extern struct clk c6x_mdio_clk;
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#endif
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#endif /* _ASM_C6X_CLOCK_H */
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