mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-26 22:24:09 +08:00
cf8de5a7f8
This is a clock driver for the simple PLLs found on Berlin SoCs. With repect to PLL registers and features, BG2/BG2CD and BG2Q are slightly different, e.g. different allowed VCO dividers and bit shifts. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
38 lines
1.1 KiB
C
38 lines
1.1 KiB
C
/*
|
|
* Copyright (c) 2014 Marvell Technology Group Ltd.
|
|
*
|
|
* Alexandre Belloni <alexandre.belloni@free-electrons.com>
|
|
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms and conditions of the GNU General Public License,
|
|
* version 2, as published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
* more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License along with
|
|
* this program. If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
#ifndef __BERLIN2_PLL_H
|
|
#define __BERLIN2_PLL_H
|
|
|
|
struct clk;
|
|
|
|
struct berlin2_pll_map {
|
|
const u8 vcodiv[16];
|
|
u8 mult;
|
|
u8 fbdiv_shift;
|
|
u8 rfdiv_shift;
|
|
u8 divsel_shift;
|
|
};
|
|
|
|
struct clk * __init
|
|
berlin2_pll_register(const struct berlin2_pll_map *map,
|
|
void __iomem *base, const char *name,
|
|
const char *parent_name, unsigned long flags);
|
|
|
|
#endif /* __BERLIN2_PLL_H */
|