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4b2b404309
Per bindings of fixed-clock, #clock-cells is a required property. Let's add it for those fixed rate clocks. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
374 lines
8.9 KiB
Plaintext
374 lines
8.9 KiB
Plaintext
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include "skeleton.dtsi"
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#include "vf610-pinfunc.h"
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#include <dt-bindings/clock/vf610-clock.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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gpio4 = &gpio5;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a5";
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device_type = "cpu";
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reg = <0x0>;
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next-level-cache = <&L2>;
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};
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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sxosc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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fxosc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&intc>;
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ranges;
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aips0: aips-bus@40000000 {
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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reg = <0x40000000 0x70000>;
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ranges;
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intc: interrupt-controller@40002000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x40003000 0x1000>,
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<0x40002100 0x100>;
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};
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L2: l2-cache@40006000 {
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compatible = "arm,pl310-cache";
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reg = <0x40006000 0x1000>;
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cache-unified;
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cache-level = <2>;
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arm,data-latency = <1 1 1>;
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arm,tag-latency = <2 2 2>;
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};
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edma0: dma-controller@40018000 {
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#dma-cells = <2>;
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compatible = "fsl,vf610-edma";
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reg = <0x40018000 0x2000>,
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<0x40024000 0x1000>,
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<0x40025000 0x1000>;
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interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
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<0 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma-tx", "edma-err";
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dma-channels = <32>;
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clock-names = "dmamux0", "dmamux1";
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clocks = <&clks VF610_CLK_DMAMUX0>,
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<&clks VF610_CLK_DMAMUX1>;
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};
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uart0: serial@40027000 {
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compatible = "fsl,vf610-lpuart";
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reg = <0x40027000 0x1000>;
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interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks VF610_CLK_UART0>;
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clock-names = "ipg";
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dmas = <&edma0 0 2>,
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<&edma0 0 3>;
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dma-names = "rx","tx";
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status = "disabled";
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};
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uart1: serial@40028000 {
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compatible = "fsl,vf610-lpuart";
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reg = <0x40028000 0x1000>;
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interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks VF610_CLK_UART1>;
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clock-names = "ipg";
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dmas = <&edma0 0 4>,
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<&edma0 0 5>;
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dma-names = "rx","tx";
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status = "disabled";
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};
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uart2: serial@40029000 {
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compatible = "fsl,vf610-lpuart";
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reg = <0x40029000 0x1000>;
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interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks VF610_CLK_UART2>;
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clock-names = "ipg";
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dmas = <&edma0 0 6>,
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<&edma0 0 7>;
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dma-names = "rx","tx";
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status = "disabled";
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};
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uart3: serial@4002a000 {
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compatible = "fsl,vf610-lpuart";
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reg = <0x4002a000 0x1000>;
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interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks VF610_CLK_UART3>;
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clock-names = "ipg";
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dmas = <&edma0 0 8>,
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<&edma0 0 9>;
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dma-names = "rx","tx";
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status = "disabled";
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};
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dspi0: dspi0@4002c000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,vf610-dspi";
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reg = <0x4002c000 0x1000>;
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interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks VF610_CLK_DSPI0>;
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clock-names = "dspi";
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spi-num-chipselects = <5>;
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status = "disabled";
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};
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sai2: sai@40031000 {
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compatible = "fsl,vf610-sai";
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reg = <0x40031000 0x1000>;
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interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks VF610_CLK_SAI2>;
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clock-names = "sai";
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dma-names = "tx", "rx";
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dmas = <&edma0 0 21>,
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<&edma0 0 20>;
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status = "disabled";
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};
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pit: pit@40037000 {
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compatible = "fsl,vf610-pit";
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reg = <0x40037000 0x1000>;
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interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks VF610_CLK_PIT>;
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clock-names = "pit";
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};
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adc0: adc@4003b000 {
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compatible = "fsl,vf610-adc";
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reg = <0x4003b000 0x1000>;
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interrupts = <0 53 0x04>;
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clocks = <&clks VF610_CLK_ADC0>;
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clock-names = "adc";
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status = "disabled";
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};
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wdog@4003e000 {
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compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
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reg = <0x4003e000 0x1000>;
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clocks = <&clks VF610_CLK_WDT>;
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clock-names = "wdog";
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};
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qspi0: quadspi@40044000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,vf610-qspi";
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reg = <0x40044000 0x1000>;
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interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks VF610_CLK_QSPI0_EN>,
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<&clks VF610_CLK_QSPI0>;
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clock-names = "qspi_en", "qspi";
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status = "disabled";
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};
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iomuxc: iomuxc@40048000 {
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compatible = "fsl,vf610-iomuxc";
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reg = <0x40048000 0x1000>;
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#gpio-range-cells = <3>;
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};
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gpio1: gpio@40049000 {
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compatible = "fsl,vf610-gpio";
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reg = <0x40049000 0x1000 0x400ff000 0x40>;
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interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&iomuxc 0 0 32>;
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};
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gpio2: gpio@4004a000 {
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compatible = "fsl,vf610-gpio";
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reg = <0x4004a000 0x1000 0x400ff040 0x40>;
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interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&iomuxc 0 32 32>;
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};
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gpio3: gpio@4004b000 {
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compatible = "fsl,vf610-gpio";
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reg = <0x4004b000 0x1000 0x400ff080 0x40>;
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interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&iomuxc 0 64 32>;
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};
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gpio4: gpio@4004c000 {
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compatible = "fsl,vf610-gpio";
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reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
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interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&iomuxc 0 96 32>;
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};
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gpio5: gpio@4004d000 {
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compatible = "fsl,vf610-gpio";
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reg = <0x4004d000 0x1000 0x400ff100 0x40>;
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interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&iomuxc 0 128 7>;
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};
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anatop@40050000 {
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compatible = "fsl,vf610-anatop";
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reg = <0x40050000 0x1000>;
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};
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i2c0: i2c@40066000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,vf610-i2c";
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reg = <0x40066000 0x1000>;
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interrupts =<0 71 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks VF610_CLK_I2C0>;
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clock-names = "ipg";
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dmas = <&edma0 0 50>,
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<&edma0 0 51>;
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dma-names = "rx","tx";
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status = "disabled";
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};
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clks: ccm@4006b000 {
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compatible = "fsl,vf610-ccm";
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reg = <0x4006b000 0x1000>;
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#clock-cells = <1>;
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};
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};
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aips1: aips-bus@40080000 {
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x40080000 0x80000>;
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ranges;
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edma1: dma-controller@40098000 {
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#dma-cells = <2>;
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compatible = "fsl,vf610-edma";
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reg = <0x40098000 0x2000>,
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<0x400a1000 0x1000>,
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<0x400a2000 0x1000>;
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interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>,
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<0 11 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma-tx", "edma-err";
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dma-channels = <32>;
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clock-names = "dmamux0", "dmamux1";
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clocks = <&clks VF610_CLK_DMAMUX2>,
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<&clks VF610_CLK_DMAMUX3>;
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};
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uart4: serial@400a9000 {
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compatible = "fsl,vf610-lpuart";
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reg = <0x400a9000 0x1000>;
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interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks VF610_CLK_UART4>;
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clock-names = "ipg";
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status = "disabled";
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};
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uart5: serial@400aa000 {
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compatible = "fsl,vf610-lpuart";
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reg = <0x400aa000 0x1000>;
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interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks VF610_CLK_UART5>;
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clock-names = "ipg";
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status = "disabled";
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};
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adc1: adc@400bb000 {
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compatible = "fsl,vf610-adc";
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reg = <0x400bb000 0x1000>;
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interrupts = <0 54 0x04>;
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clocks = <&clks VF610_CLK_ADC1>;
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clock-names = "adc";
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status = "disabled";
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};
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fec0: ethernet@400d0000 {
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compatible = "fsl,mvf600-fec";
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reg = <0x400d0000 0x1000>;
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interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks VF610_CLK_ENET0>,
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<&clks VF610_CLK_ENET0>,
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<&clks VF610_CLK_ENET>;
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clock-names = "ipg", "ahb", "ptp";
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status = "disabled";
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};
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fec1: ethernet@400d1000 {
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compatible = "fsl,mvf600-fec";
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reg = <0x400d1000 0x1000>;
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interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks VF610_CLK_ENET1>,
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<&clks VF610_CLK_ENET1>,
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<&clks VF610_CLK_ENET>;
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clock-names = "ipg", "ahb", "ptp";
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status = "disabled";
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};
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};
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};
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};
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