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2c8086a5d0
Signed-off-by: eric miao <eric.y.miao@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
76 lines
3.1 KiB
C
76 lines
3.1 KiB
C
/*
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* linux/include/asm-arm/arch-pxa/pxa3xx-regs.h
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*
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* PXA3xx specific register definitions
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*
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* Copyright (C) 2007 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_PXA3XX_REGS_H
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#define __ASM_ARCH_PXA3XX_REGS_H
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/*
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* Application Subsystem Clock
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*/
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#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */
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#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */
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#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */
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#define CKENA __REG(0x4134000C) /* A Clock Enable Register */
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#define CKENB __REG(0x41340010) /* B Clock Enable Register */
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#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */
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/*
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* Clock Enable Bit
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*/
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#define CKEN_LCD 1 /* < LCD Clock Enable */
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#define CKEN_USBH 2 /* < USB host clock enable */
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#define CKEN_CAMERA 3 /* < Camera interface clock enable */
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#define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */
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#define CKEN_USB2 6 /* < USB 2.0 client clock enable. */
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#define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */
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#define CKEN_SMC 9 /* < Static Memory Controller clock enable */
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#define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */
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#define CKEN_BOOT 11 /* < Boot rom clock enable */
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#define CKEN_MMC1 12 /* < MMC1 Clock enable */
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#define CKEN_MMC2 13 /* < MMC2 clock enable */
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#define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */
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#define CKEN_CIR 15 /* < Consumer IR Clock Enable */
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#define CKEN_USIM0 17 /* < USIM[0] Clock Enable */
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#define CKEN_USIM1 18 /* < USIM[1] Clock Enable */
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#define CKEN_TPM 19 /* < TPM clock enable */
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#define CKEN_UDC 20 /* < UDC clock enable */
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#define CKEN_BTUART 21 /* < BTUART clock enable */
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#define CKEN_FFUART 22 /* < FFUART clock enable */
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#define CKEN_STUART 23 /* < STUART clock enable */
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#define CKEN_AC97 24 /* < AC97 clock enable */
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#define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */
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#define CKEN_SSP1 26 /* < SSP1 clock enable */
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#define CKEN_SSP2 27 /* < SSP2 clock enable */
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#define CKEN_SSP3 28 /* < SSP3 clock enable */
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#define CKEN_SSP4 29 /* < SSP4 clock enable */
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#define CKEN_MSL0 30 /* < MSL0 clock enable */
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#define CKEN_PWM0 32 /* < PWM[0] clock enable */
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#define CKEN_PWM1 33 /* < PWM[1] clock enable */
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#define CKEN_I2C 36 /* < I2C clock enable */
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#define CKEN_INTC 38 /* < Interrupt controller clock enable */
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#define CKEN_GPIO 39 /* < GPIO clock enable */
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#define CKEN_1WIRE 40 /* < 1-wire clock enable */
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#define CKEN_HSIO2 41 /* < HSIO2 clock enable */
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#define CKEN_MINI_IM 48 /* < Mini-IM */
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#define CKEN_MINI_LCD 49 /* < Mini LCD */
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#if defined(CONFIG_CPU_PXA310)
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#define CKEN_MMC3 5 /* < MMC3 Clock Enable */
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#define CKEN_MVED 43 /* < MVED clock enable */
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#endif
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/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
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#define PXA300_CKEN_GRAPHICS 42 /* Graphics controller clock enable */
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#define PXA320_CKEN_GRAPHICS 7 /* Graphics controller clock enable */
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#endif /* __ASM_ARCH_PXA3XX_REGS_H */
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