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6ebbf2ce43
ARMv6 and greater introduced a new instruction ("bx") which can be used
to return from function calls. Recent CPUs perform better when the
"bx lr" instruction is used rather than the "mov pc, lr" instruction,
and this sequence is strongly recommended to be used by the ARM
architecture manual (section A.4.1.1).
We provide a new macro "ret" with all its variants for the condition
code which will resolve to the appropriate instruction.
Rather than doing this piecemeal, and miss some instances, change all
the "mov pc" instances to use the new macro, with the exception of
the "movs" instruction and the kprobes code. This allows us to detect
the "mov pc, lr" case and fix it up - and also gives us the possibility
of deploying this for other registers depending on the CPU selection.
Reported-by: Will Deacon <will.deacon@arm.com>
Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701_bootresume.S
Tested-by: Andrew Lunn <andrew@lunn.ch> # Kirkwood
Tested-by: Shawn Guo <shawn.guo@freescale.com>
Tested-by: Tony Lindgren <tony@atomide.com> # OMAPs
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> # Armada XP, 375, 385
Acked-by: Sekhar Nori <nsekhar@ti.com> # DaVinci
Acked-by: Christoffer Dall <christoffer.dall@linaro.org> # kvm/hyp
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> # PXA3xx
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> # Xen
Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> # ARMv7M
Tested-by: Simon Horman <horms+renesas@verge.net.au> # Shmobile
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
52 lines
1.3 KiB
ArmAsm
52 lines
1.3 KiB
ArmAsm
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include "proc-macros.S"
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ENTRY(nop_flush_icache_all)
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ret lr
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ENDPROC(nop_flush_icache_all)
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.globl nop_flush_kern_cache_all
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.equ nop_flush_kern_cache_all, nop_flush_icache_all
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.globl nop_flush_kern_cache_louis
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.equ nop_flush_kern_cache_louis, nop_flush_icache_all
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.globl nop_flush_user_cache_all
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.equ nop_flush_user_cache_all, nop_flush_icache_all
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.globl nop_flush_user_cache_range
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.equ nop_flush_user_cache_range, nop_flush_icache_all
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.globl nop_coherent_kern_range
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.equ nop_coherent_kern_range, nop_flush_icache_all
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ENTRY(nop_coherent_user_range)
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mov r0, 0
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ret lr
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ENDPROC(nop_coherent_user_range)
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.globl nop_flush_kern_dcache_area
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.equ nop_flush_kern_dcache_area, nop_flush_icache_all
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.globl nop_dma_flush_range
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.equ nop_dma_flush_range, nop_flush_icache_all
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.globl nop_dma_map_area
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.equ nop_dma_map_area, nop_flush_icache_all
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.globl nop_dma_unmap_area
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.equ nop_dma_unmap_area, nop_flush_icache_all
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__INITDATA
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@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
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define_cache_functions nop
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