mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-25 21:54:06 +08:00
297d716f62
Change the ownership of power_supply structure from each driver
implementing the class to the power supply core.
The patch changes power_supply_register() function thus all drivers
implementing power supply class are adjusted.
Each driver provides the implementation of power supply. However it
should not be the owner of power supply class instance because it is
exposed by core to other subsystems with power_supply_get_by_name().
These other subsystems have no knowledge when the driver will unregister
the power supply. This leads to several issues when driver is unbound -
mostly because user of power supply accesses freed memory.
Instead let the core own the instance of struct 'power_supply'. Other
users of this power supply will still access valid memory because it
will be freed when device reference count reaches 0. Currently this
means "it will leak" but power_supply_put() call in next patches will
solve it.
This solves invalid memory references in following race condition
scenario:
Thread 1: charger manager
Thread 2: power supply driver, used by charger manager
THREAD 1 (charger manager) THREAD 2 (power supply driver)
========================== ==============================
psy = power_supply_get_by_name()
Driver unbind, .remove
power_supply_unregister()
Device fully removed
psy->get_property()
The 'get_property' call is executed in invalid context because the driver was
unbound and struct 'power_supply' memory was freed.
This could be observed easily with charger manager driver (here compiled
with max17040 fuel gauge):
$ cat /sys/devices/virtual/power_supply/cm-battery/capacity &
$ echo "1-0036" > /sys/bus/i2c/drivers/max17040/unbind
[ 55.725123] Unable to handle kernel NULL pointer dereference at virtual address 00000000
[ 55.732584] pgd = d98d4000
[ 55.734060] [00000000] *pgd=5afa2831, *pte=00000000, *ppte=00000000
[ 55.740318] Internal error: Oops: 80000007 [#1] PREEMPT SMP ARM
[ 55.746210] Modules linked in:
[ 55.749259] CPU: 1 PID: 2936 Comm: cat Tainted: G W 3.19.0-rc1-next-20141226-00048-gf79f475f3c44-dirty #1496
[ 55.760190] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
[ 55.766270] task: d9b76f00 ti: daf54000 task.ti: daf54000
[ 55.771647] PC is at 0x0
[ 55.774182] LR is at charger_get_property+0x2f4/0x36c
[ 55.779201] pc : [<00000000>] lr : [<c034b0b4>] psr: 60000013
[ 55.779201] sp : daf55e90 ip : 00000003 fp : 00000000
[ 55.790657] r10: 00000000 r9 : c06e2878 r8 : d9b26c68
[ 55.795865] r7 : dad81610 r6 : daec7410 r5 : daf55ebc r4 : 00000000
[ 55.802367] r3 : 00000000 r2 : daf55ebc r1 : 0000002a r0 : d9b26c68
[ 55.808879] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user
[ 55.815994] Control: 10c5387d Table: 598d406a DAC: 00000015
[ 55.821723] Process cat (pid: 2936, stack limit = 0xdaf54210)
[ 55.827451] Stack: (0xdaf55e90 to 0xdaf56000)
[ 55.831795] 5e80: 60000013 c01459c4 0000002a c06f8ef8
[ 55.839956] 5ea0: db651000 c06f8ef8 daebac00 c04cb668 daebac08 c0346864 00000000 c01459c4
[ 55.848115] 5ec0: d99eaa80 c06f8ef8 00000fff 00001000 db651000 c027f25c c027f240 d99eaa80
[ 55.856274] 5ee0: d9a06c00 c0146218 daf55f18 00001000 d99eaa80 db4c18c0 00000001 00000001
[ 55.864468] 5f00: daf55f80 c0144c78 c0144c54 c0107f90 00015000 d99eaab0 00000000 00000000
[ 55.872603] 5f20: 000051c7 00000000 db4c18c0 c04a9370 00015000 00001000 daf55f80 00001000
[ 55.880763] 5f40: daf54000 00015000 00000000 c00e53dc db4c18c0 c00e548c 0000000d 00008124
[ 55.888937] 5f60: 00000001 00000000 00000000 db4c18c0 db4c18c0 00001000 00015000 c00e5550
[ 55.897099] 5f80: 00000000 00000000 00001000 00001000 00015000 00000003 00000003 c000f364
[ 55.905239] 5fa0: 00000000 c000f1a0 00001000 00015000 00000003 00015000 00001000 0001333c
[ 55.913399] 5fc0: 00001000 00015000 00000003 00000003 00000002 00000000 00000000 00000000
[ 55.921560] 5fe0: 7fffe000 be999850 0000a225 b6f3c19c 60000010 00000003 00000000 00000000
[ 55.929744] [<c034b0b4>] (charger_get_property) from [<c0346864>] (power_supply_show_property+0x48/0x20c)
[ 55.939286] [<c0346864>] (power_supply_show_property) from [<c027f25c>] (dev_attr_show+0x1c/0x48)
[ 55.948130] [<c027f25c>] (dev_attr_show) from [<c0146218>] (sysfs_kf_seq_show+0x84/0x104)
[ 55.956298] [<c0146218>] (sysfs_kf_seq_show) from [<c0144c78>] (kernfs_seq_show+0x24/0x28)
[ 55.964536] [<c0144c78>] (kernfs_seq_show) from [<c0107f90>] (seq_read+0x1b0/0x484)
[ 55.972172] [<c0107f90>] (seq_read) from [<c00e53dc>] (__vfs_read+0x18/0x4c)
[ 55.979188] [<c00e53dc>] (__vfs_read) from [<c00e548c>] (vfs_read+0x7c/0x100)
[ 55.986304] [<c00e548c>] (vfs_read) from [<c00e5550>] (SyS_read+0x40/0x8c)
[ 55.993164] [<c00e5550>] (SyS_read) from [<c000f1a0>] (ret_fast_syscall+0x0/0x48)
[ 56.000626] Code: bad PC value
[ 56.011652] ---[ end trace 7b64343fbdae8ef1 ]---
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
[for the nvec part]
Reviewed-by: Marc Dietrich <marvin24@gmx.de>
[for compal-laptop.c]
Acked-by: Darren Hart <dvhart@linux.intel.com>
[for the mfd part]
Acked-by: Lee Jones <lee.jones@linaro.org>
[for the hid part]
Acked-by: Jiri Kosina <jkosina@suse.cz>
[for the acpi part]
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Sebastian Reichel <sre@kernel.org>
494 lines
14 KiB
C
494 lines
14 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2012
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*
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* PM2301 power supply interface
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*
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* License terms: GNU General Public License (GPL), version 2
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*/
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#ifndef PM2301_CHARGER_H
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#define PM2301_CHARGER_H
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/* Watchdog timeout constant */
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#define WD_TIMER 0x30 /* 4min */
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#define WD_KICK_INTERVAL (30 * HZ)
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#define PM2XXX_NUM_INT_REG 0x6
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/* Constant voltage/current */
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#define PM2XXX_CONST_CURR 0x0
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#define PM2XXX_CONST_VOLT 0x1
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/* Lowest charger voltage is 3.39V -> 0x4E */
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#define LOW_VOLT_REG 0x4E
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#define PM2XXX_BATT_CTRL_REG1 0x00
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#define PM2XXX_BATT_CTRL_REG2 0x01
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#define PM2XXX_BATT_CTRL_REG3 0x02
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#define PM2XXX_BATT_CTRL_REG4 0x03
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#define PM2XXX_BATT_CTRL_REG5 0x04
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#define PM2XXX_BATT_CTRL_REG6 0x05
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#define PM2XXX_BATT_CTRL_REG7 0x06
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#define PM2XXX_BATT_CTRL_REG8 0x07
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#define PM2XXX_NTC_CTRL_REG1 0x08
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#define PM2XXX_NTC_CTRL_REG2 0x09
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#define PM2XXX_BATT_CTRL_REG9 0x0A
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#define PM2XXX_BATT_STAT_REG1 0x0B
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#define PM2XXX_INP_VOLT_VPWR2 0x11
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#define PM2XXX_INP_DROP_VPWR2 0x13
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#define PM2XXX_INP_VOLT_VPWR1 0x15
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#define PM2XXX_INP_DROP_VPWR1 0x17
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#define PM2XXX_INP_MODE_VPWR 0x18
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#define PM2XXX_BATT_WD_KICK 0x70
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#define PM2XXX_DEV_VER_STAT 0x0C
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#define PM2XXX_THERM_WARN_CTRL_REG 0x20
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#define PM2XXX_BATT_DISC_REG 0x21
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#define PM2XXX_BATT_LOW_LEV_COMP_REG 0x22
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#define PM2XXX_BATT_LOW_LEV_VAL_REG 0x23
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#define PM2XXX_I2C_PAD_CTRL_REG 0x24
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#define PM2XXX_SW_CTRL_REG 0x26
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#define PM2XXX_LED_CTRL_REG 0x28
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#define PM2XXX_REG_INT1 0x40
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#define PM2XXX_MASK_REG_INT1 0x50
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#define PM2XXX_SRCE_REG_INT1 0x60
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#define PM2XXX_REG_INT2 0x41
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#define PM2XXX_MASK_REG_INT2 0x51
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#define PM2XXX_SRCE_REG_INT2 0x61
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#define PM2XXX_REG_INT3 0x42
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#define PM2XXX_MASK_REG_INT3 0x52
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#define PM2XXX_SRCE_REG_INT3 0x62
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#define PM2XXX_REG_INT4 0x43
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#define PM2XXX_MASK_REG_INT4 0x53
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#define PM2XXX_SRCE_REG_INT4 0x63
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#define PM2XXX_REG_INT5 0x44
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#define PM2XXX_MASK_REG_INT5 0x54
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#define PM2XXX_SRCE_REG_INT5 0x64
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#define PM2XXX_REG_INT6 0x45
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#define PM2XXX_MASK_REG_INT6 0x55
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#define PM2XXX_SRCE_REG_INT6 0x65
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#define VPWR_OVV 0x0
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#define VSYSTEM_OVV 0x1
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/* control Reg 1 */
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#define PM2XXX_CH_RESUME_EN 0x1
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#define PM2XXX_CH_RESUME_DIS 0x0
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/* control Reg 2 */
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#define PM2XXX_CH_AUTO_RESUME_EN 0X2
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#define PM2XXX_CH_AUTO_RESUME_DIS 0X0
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#define PM2XXX_CHARGER_ENA 0x4
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#define PM2XXX_CHARGER_DIS 0x0
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/* control Reg 3 */
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#define PM2XXX_CH_WD_CC_PHASE_OFF 0x0
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#define PM2XXX_CH_WD_CC_PHASE_5MIN 0x1
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#define PM2XXX_CH_WD_CC_PHASE_10MIN 0x2
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#define PM2XXX_CH_WD_CC_PHASE_30MIN 0x3
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#define PM2XXX_CH_WD_CC_PHASE_60MIN 0x4
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#define PM2XXX_CH_WD_CC_PHASE_120MIN 0x5
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#define PM2XXX_CH_WD_CC_PHASE_240MIN 0x6
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#define PM2XXX_CH_WD_CC_PHASE_360MIN 0x7
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#define PM2XXX_CH_WD_CV_PHASE_OFF (0x0<<3)
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#define PM2XXX_CH_WD_CV_PHASE_5MIN (0x1<<3)
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#define PM2XXX_CH_WD_CV_PHASE_10MIN (0x2<<3)
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#define PM2XXX_CH_WD_CV_PHASE_30MIN (0x3<<3)
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#define PM2XXX_CH_WD_CV_PHASE_60MIN (0x4<<3)
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#define PM2XXX_CH_WD_CV_PHASE_120MIN (0x5<<3)
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#define PM2XXX_CH_WD_CV_PHASE_240MIN (0x6<<3)
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#define PM2XXX_CH_WD_CV_PHASE_360MIN (0x7<<3)
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/* control Reg 4 */
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#define PM2XXX_CH_WD_PRECH_PHASE_OFF 0x0
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#define PM2XXX_CH_WD_PRECH_PHASE_1MIN 0x1
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#define PM2XXX_CH_WD_PRECH_PHASE_5MIN 0x2
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#define PM2XXX_CH_WD_PRECH_PHASE_10MIN 0x3
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#define PM2XXX_CH_WD_PRECH_PHASE_30MIN 0x4
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#define PM2XXX_CH_WD_PRECH_PHASE_60MIN 0x5
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#define PM2XXX_CH_WD_PRECH_PHASE_120MIN 0x6
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#define PM2XXX_CH_WD_PRECH_PHASE_240MIN 0x7
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/* control Reg 5 */
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#define PM2XXX_CH_WD_AUTO_TIMEOUT_NONE 0x0
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#define PM2XXX_CH_WD_AUTO_TIMEOUT_20MIN 0x1
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/* control Reg 6 */
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#define PM2XXX_DIR_CH_CC_CURRENT_MASK 0x0F
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#define PM2XXX_DIR_CH_CC_CURRENT_200MA 0x0
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#define PM2XXX_DIR_CH_CC_CURRENT_400MA 0x2
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#define PM2XXX_DIR_CH_CC_CURRENT_600MA 0x3
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#define PM2XXX_DIR_CH_CC_CURRENT_800MA 0x4
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#define PM2XXX_DIR_CH_CC_CURRENT_1000MA 0x5
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#define PM2XXX_DIR_CH_CC_CURRENT_1200MA 0x6
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#define PM2XXX_DIR_CH_CC_CURRENT_1400MA 0x7
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#define PM2XXX_DIR_CH_CC_CURRENT_1600MA 0x8
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#define PM2XXX_DIR_CH_CC_CURRENT_1800MA 0x9
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#define PM2XXX_DIR_CH_CC_CURRENT_2000MA 0xA
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#define PM2XXX_DIR_CH_CC_CURRENT_2200MA 0xB
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#define PM2XXX_DIR_CH_CC_CURRENT_2400MA 0xC
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#define PM2XXX_DIR_CH_CC_CURRENT_2600MA 0xD
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#define PM2XXX_DIR_CH_CC_CURRENT_2800MA 0xE
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#define PM2XXX_DIR_CH_CC_CURRENT_3000MA 0xF
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#define PM2XXX_CH_PRECH_CURRENT_MASK 0x30
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#define PM2XXX_CH_PRECH_CURRENT_25MA (0x0<<4)
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#define PM2XXX_CH_PRECH_CURRENT_50MA (0x1<<4)
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#define PM2XXX_CH_PRECH_CURRENT_75MA (0x2<<4)
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#define PM2XXX_CH_PRECH_CURRENT_100MA (0x3<<4)
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#define PM2XXX_CH_EOC_CURRENT_MASK 0xC0
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#define PM2XXX_CH_EOC_CURRENT_100MA (0x0<<6)
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#define PM2XXX_CH_EOC_CURRENT_150MA (0x1<<6)
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#define PM2XXX_CH_EOC_CURRENT_300MA (0x2<<6)
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#define PM2XXX_CH_EOC_CURRENT_400MA (0x3<<6)
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/* control Reg 7 */
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#define PM2XXX_CH_PRECH_VOL_2_5 0x0
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#define PM2XXX_CH_PRECH_VOL_2_7 0x1
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#define PM2XXX_CH_PRECH_VOL_2_9 0x2
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#define PM2XXX_CH_PRECH_VOL_3_1 0x3
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#define PM2XXX_CH_VRESUME_VOL_3_2 (0x0<<2)
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#define PM2XXX_CH_VRESUME_VOL_3_4 (0x1<<2)
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#define PM2XXX_CH_VRESUME_VOL_3_6 (0x2<<2)
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#define PM2XXX_CH_VRESUME_VOL_3_8 (0x3<<2)
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/* control Reg 8 */
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#define PM2XXX_CH_VOLT_MASK 0x3F
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#define PM2XXX_CH_VOLT_3_5 0x0
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#define PM2XXX_CH_VOLT_3_5225 0x1
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#define PM2XXX_CH_VOLT_3_6 0x4
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#define PM2XXX_CH_VOLT_3_7 0x8
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#define PM2XXX_CH_VOLT_4_0 0x14
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#define PM2XXX_CH_VOLT_4_175 0x1B
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#define PM2XXX_CH_VOLT_4_2 0x1C
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#define PM2XXX_CH_VOLT_4_275 0x1F
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#define PM2XXX_CH_VOLT_4_3 0x20
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/*NTC control register 1*/
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#define PM2XXX_BTEMP_HIGH_TH_45 0x0
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#define PM2XXX_BTEMP_HIGH_TH_50 0x1
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#define PM2XXX_BTEMP_HIGH_TH_55 0x2
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#define PM2XXX_BTEMP_HIGH_TH_60 0x3
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#define PM2XXX_BTEMP_HIGH_TH_65 0x4
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#define PM2XXX_BTEMP_LOW_TH_N5 (0x0<<3)
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#define PM2XXX_BTEMP_LOW_TH_0 (0x1<<3)
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#define PM2XXX_BTEMP_LOW_TH_5 (0x2<<3)
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#define PM2XXX_BTEMP_LOW_TH_10 (0x3<<3)
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/*NTC control register 2*/
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#define PM2XXX_NTC_BETA_COEFF_3477 0x0
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#define PM2XXX_NTC_BETA_COEFF_3964 0x1
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#define PM2XXX_NTC_RES_10K (0x0<<2)
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#define PM2XXX_NTC_RES_47K (0x1<<2)
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#define PM2XXX_NTC_RES_100K (0x2<<2)
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#define PM2XXX_NTC_RES_NO_NTC (0x3<<2)
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/* control Reg 9 */
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#define PM2XXX_CH_CC_MODEDROP_EN 1
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#define PM2XXX_CH_CC_MODEDROP_DIS 0
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#define PM2XXX_CH_CC_REDUCED_CURRENT_100MA (0x0<<1)
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#define PM2XXX_CH_CC_REDUCED_CURRENT_200MA (0x1<<1)
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#define PM2XXX_CH_CC_REDUCED_CURRENT_400MA (0x2<<1)
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#define PM2XXX_CH_CC_REDUCED_CURRENT_IDENT (0x3<<1)
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#define PM2XXX_CHARCHING_INFO_DIS (0<<3)
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#define PM2XXX_CHARCHING_INFO_EN (1<<3)
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#define PM2XXX_CH_150MV_DROP_300MV (0<<4)
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#define PM2XXX_CH_150MV_DROP_150MV (1<<4)
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/* charger status register */
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#define PM2XXX_CHG_STATUS_OFF 0x0
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#define PM2XXX_CHG_STATUS_ON 0x1
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#define PM2XXX_CHG_STATUS_FULL 0x2
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#define PM2XXX_CHG_STATUS_ERR 0x3
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#define PM2XXX_CHG_STATUS_WAIT 0x4
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#define PM2XXX_CHG_STATUS_NOBAT 0x5
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/* Input charger voltage VPWR2 */
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#define PM2XXX_VPWR2_OVV_6_0 0x0
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#define PM2XXX_VPWR2_OVV_6_3 0x1
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#define PM2XXX_VPWR2_OVV_10 0x2
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#define PM2XXX_VPWR2_OVV_NONE 0x3
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/* Input charger drop VPWR2 */
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#define PM2XXX_VPWR2_HW_OPT_EN (0x1<<4)
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#define PM2XXX_VPWR2_HW_OPT_DIS (0x0<<4)
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#define PM2XXX_VPWR2_VALID_EN (0x1<<3)
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#define PM2XXX_VPWR2_VALID_DIS (0x0<<3)
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#define PM2XXX_VPWR2_DROP_EN (0x1<<2)
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#define PM2XXX_VPWR2_DROP_DIS (0x0<<2)
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/* Input charger voltage VPWR1 */
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#define PM2XXX_VPWR1_OVV_6_0 0x0
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#define PM2XXX_VPWR1_OVV_6_3 0x1
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#define PM2XXX_VPWR1_OVV_10 0x2
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#define PM2XXX_VPWR1_OVV_NONE 0x3
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/* Input charger drop VPWR1 */
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#define PM2XXX_VPWR1_HW_OPT_EN (0x1<<4)
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#define PM2XXX_VPWR1_HW_OPT_DIS (0x0<<4)
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#define PM2XXX_VPWR1_VALID_EN (0x1<<3)
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#define PM2XXX_VPWR1_VALID_DIS (0x0<<3)
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#define PM2XXX_VPWR1_DROP_EN (0x1<<2)
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#define PM2XXX_VPWR1_DROP_DIS (0x0<<2)
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/* Battery low level comparator control register */
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#define PM2XXX_VBAT_LOW_MONITORING_DIS 0x0
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#define PM2XXX_VBAT_LOW_MONITORING_ENA 0x1
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/* Battery low level value control register */
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#define PM2XXX_VBAT_LOW_LEVEL_2_3 0x0
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#define PM2XXX_VBAT_LOW_LEVEL_2_4 0x1
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#define PM2XXX_VBAT_LOW_LEVEL_2_5 0x2
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#define PM2XXX_VBAT_LOW_LEVEL_2_6 0x3
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#define PM2XXX_VBAT_LOW_LEVEL_2_7 0x4
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#define PM2XXX_VBAT_LOW_LEVEL_2_8 0x5
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#define PM2XXX_VBAT_LOW_LEVEL_2_9 0x6
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#define PM2XXX_VBAT_LOW_LEVEL_3_0 0x7
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#define PM2XXX_VBAT_LOW_LEVEL_3_1 0x8
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#define PM2XXX_VBAT_LOW_LEVEL_3_2 0x9
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#define PM2XXX_VBAT_LOW_LEVEL_3_3 0xA
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#define PM2XXX_VBAT_LOW_LEVEL_3_4 0xB
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#define PM2XXX_VBAT_LOW_LEVEL_3_5 0xC
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#define PM2XXX_VBAT_LOW_LEVEL_3_6 0xD
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#define PM2XXX_VBAT_LOW_LEVEL_3_7 0xE
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#define PM2XXX_VBAT_LOW_LEVEL_3_8 0xF
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#define PM2XXX_VBAT_LOW_LEVEL_3_9 0x10
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#define PM2XXX_VBAT_LOW_LEVEL_4_0 0x11
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#define PM2XXX_VBAT_LOW_LEVEL_4_1 0x12
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#define PM2XXX_VBAT_LOW_LEVEL_4_2 0x13
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/* SW CTRL */
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#define PM2XXX_SWCTRL_HW 0x0
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#define PM2XXX_SWCTRL_SW 0x1
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/* LED Driver Control */
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#define PM2XXX_LED_CURRENT_MASK 0x0C
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#define PM2XXX_LED_CURRENT_2_5MA (0X0<<2)
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#define PM2XXX_LED_CURRENT_1MA (0X1<<2)
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#define PM2XXX_LED_CURRENT_5MA (0X2<<2)
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#define PM2XXX_LED_CURRENT_10MA (0X3<<2)
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#define PM2XXX_LED_SELECT_MASK 0x02
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#define PM2XXX_LED_SELECT_EN (0X0<<1)
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#define PM2XXX_LED_SELECT_DIS (0X1<<1)
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#define PM2XXX_ANTI_OVERSHOOT_MASK 0x01
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#define PM2XXX_ANTI_OVERSHOOT_DIS 0X0
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#define PM2XXX_ANTI_OVERSHOOT_EN 0X1
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enum pm2xxx_reg_int1 {
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PM2XXX_INT1_ITVBATDISCONNECT = 0x02,
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PM2XXX_INT1_ITVBATLOWR = 0x04,
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PM2XXX_INT1_ITVBATLOWF = 0x08,
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};
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enum pm2xxx_mask_reg_int1 {
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PM2XXX_INT1_M_ITVBATDISCONNECT = 0x02,
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PM2XXX_INT1_M_ITVBATLOWR = 0x04,
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PM2XXX_INT1_M_ITVBATLOWF = 0x08,
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};
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enum pm2xxx_source_reg_int1 {
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PM2XXX_INT1_S_ITVBATDISCONNECT = 0x02,
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PM2XXX_INT1_S_ITVBATLOWR = 0x04,
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PM2XXX_INT1_S_ITVBATLOWF = 0x08,
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};
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enum pm2xxx_reg_int2 {
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PM2XXX_INT2_ITVPWR2PLUG = 0x01,
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PM2XXX_INT2_ITVPWR2UNPLUG = 0x02,
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PM2XXX_INT2_ITVPWR1PLUG = 0x04,
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PM2XXX_INT2_ITVPWR1UNPLUG = 0x08,
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};
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enum pm2xxx_mask_reg_int2 {
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PM2XXX_INT2_M_ITVPWR2PLUG = 0x01,
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PM2XXX_INT2_M_ITVPWR2UNPLUG = 0x02,
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PM2XXX_INT2_M_ITVPWR1PLUG = 0x04,
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PM2XXX_INT2_M_ITVPWR1UNPLUG = 0x08,
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};
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enum pm2xxx_source_reg_int2 {
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PM2XXX_INT2_S_ITVPWR2PLUG = 0x03,
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PM2XXX_INT2_S_ITVPWR1PLUG = 0x0c,
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};
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enum pm2xxx_reg_int3 {
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PM2XXX_INT3_ITCHPRECHARGEWD = 0x01,
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PM2XXX_INT3_ITCHCCWD = 0x02,
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PM2XXX_INT3_ITCHCVWD = 0x04,
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PM2XXX_INT3_ITAUTOTIMEOUTWD = 0x08,
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};
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enum pm2xxx_mask_reg_int3 {
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PM2XXX_INT3_M_ITCHPRECHARGEWD = 0x01,
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PM2XXX_INT3_M_ITCHCCWD = 0x02,
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PM2XXX_INT3_M_ITCHCVWD = 0x04,
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PM2XXX_INT3_M_ITAUTOTIMEOUTWD = 0x08,
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};
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enum pm2xxx_source_reg_int3 {
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PM2XXX_INT3_S_ITCHPRECHARGEWD = 0x01,
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PM2XXX_INT3_S_ITCHCCWD = 0x02,
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PM2XXX_INT3_S_ITCHCVWD = 0x04,
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PM2XXX_INT3_S_ITAUTOTIMEOUTWD = 0x08,
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};
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enum pm2xxx_reg_int4 {
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PM2XXX_INT4_ITBATTEMPCOLD = 0x01,
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PM2XXX_INT4_ITBATTEMPHOT = 0x02,
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PM2XXX_INT4_ITVPWR2OVV = 0x04,
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PM2XXX_INT4_ITVPWR1OVV = 0x08,
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PM2XXX_INT4_ITCHARGINGON = 0x10,
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PM2XXX_INT4_ITVRESUME = 0x20,
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PM2XXX_INT4_ITBATTFULL = 0x40,
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PM2XXX_INT4_ITCVPHASE = 0x80,
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};
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enum pm2xxx_mask_reg_int4 {
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PM2XXX_INT4_M_ITBATTEMPCOLD = 0x01,
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PM2XXX_INT4_M_ITBATTEMPHOT = 0x02,
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PM2XXX_INT4_M_ITVPWR2OVV = 0x04,
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PM2XXX_INT4_M_ITVPWR1OVV = 0x08,
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PM2XXX_INT4_M_ITCHARGINGON = 0x10,
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PM2XXX_INT4_M_ITVRESUME = 0x20,
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PM2XXX_INT4_M_ITBATTFULL = 0x40,
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PM2XXX_INT4_M_ITCVPHASE = 0x80,
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};
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enum pm2xxx_source_reg_int4 {
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PM2XXX_INT4_S_ITBATTEMPCOLD = 0x01,
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PM2XXX_INT4_S_ITBATTEMPHOT = 0x02,
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PM2XXX_INT4_S_ITVPWR2OVV = 0x04,
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PM2XXX_INT4_S_ITVPWR1OVV = 0x08,
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PM2XXX_INT4_S_ITCHARGINGON = 0x10,
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PM2XXX_INT4_S_ITVRESUME = 0x20,
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PM2XXX_INT4_S_ITBATTFULL = 0x40,
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PM2XXX_INT4_S_ITCVPHASE = 0x80,
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};
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enum pm2xxx_reg_int5 {
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PM2XXX_INT5_ITTHERMALSHUTDOWNRISE = 0x01,
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PM2XXX_INT5_ITTHERMALSHUTDOWNFALL = 0x02,
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PM2XXX_INT5_ITTHERMALWARNINGRISE = 0x04,
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PM2XXX_INT5_ITTHERMALWARNINGFALL = 0x08,
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PM2XXX_INT5_ITVSYSTEMOVV = 0x10,
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};
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enum pm2xxx_mask_reg_int5 {
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PM2XXX_INT5_M_ITTHERMALSHUTDOWNRISE = 0x01,
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PM2XXX_INT5_M_ITTHERMALSHUTDOWNFALL = 0x02,
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PM2XXX_INT5_M_ITTHERMALWARNINGRISE = 0x04,
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PM2XXX_INT5_M_ITTHERMALWARNINGFALL = 0x08,
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PM2XXX_INT5_M_ITVSYSTEMOVV = 0x10,
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};
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enum pm2xxx_source_reg_int5 {
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PM2XXX_INT5_S_ITTHERMALSHUTDOWNRISE = 0x01,
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PM2XXX_INT5_S_ITTHERMALSHUTDOWNFALL = 0x02,
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PM2XXX_INT5_S_ITTHERMALWARNINGRISE = 0x04,
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PM2XXX_INT5_S_ITTHERMALWARNINGFALL = 0x08,
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PM2XXX_INT5_S_ITVSYSTEMOVV = 0x10,
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};
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enum pm2xxx_reg_int6 {
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PM2XXX_INT6_ITVPWR2DROP = 0x01,
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PM2XXX_INT6_ITVPWR1DROP = 0x02,
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PM2XXX_INT6_ITVPWR2VALIDRISE = 0x04,
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PM2XXX_INT6_ITVPWR2VALIDFALL = 0x08,
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PM2XXX_INT6_ITVPWR1VALIDRISE = 0x10,
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PM2XXX_INT6_ITVPWR1VALIDFALL = 0x20,
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};
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enum pm2xxx_mask_reg_int6 {
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PM2XXX_INT6_M_ITVPWR2DROP = 0x01,
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PM2XXX_INT6_M_ITVPWR1DROP = 0x02,
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PM2XXX_INT6_M_ITVPWR2VALIDRISE = 0x04,
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PM2XXX_INT6_M_ITVPWR2VALIDFALL = 0x08,
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PM2XXX_INT6_M_ITVPWR1VALIDRISE = 0x10,
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PM2XXX_INT6_M_ITVPWR1VALIDFALL = 0x20,
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};
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enum pm2xxx_source_reg_int6 {
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PM2XXX_INT6_S_ITVPWR2DROP = 0x01,
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PM2XXX_INT6_S_ITVPWR1DROP = 0x02,
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PM2XXX_INT6_S_ITVPWR2VALIDRISE = 0x04,
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PM2XXX_INT6_S_ITVPWR2VALIDFALL = 0x08,
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PM2XXX_INT6_S_ITVPWR1VALIDRISE = 0x10,
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PM2XXX_INT6_S_ITVPWR1VALIDFALL = 0x20,
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};
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struct pm2xxx_charger_info {
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int charger_connected;
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int charger_online;
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int cv_active;
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bool wd_expired;
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};
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struct pm2xxx_charger_event_flags {
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bool mainextchnotok;
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bool main_thermal_prot;
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bool ovv;
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bool chgwdexp;
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};
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struct pm2xxx_interrupts {
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u8 reg[PM2XXX_NUM_INT_REG];
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int (*handler[PM2XXX_NUM_INT_REG])(void *, int);
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};
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struct pm2xxx_config {
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struct i2c_client *pm2xxx_i2c;
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struct i2c_device_id *pm2xxx_id;
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};
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struct pm2xxx_irq {
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char *name;
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irqreturn_t (*isr)(int irq, void *data);
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};
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struct pm2xxx_charger {
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struct device *dev;
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u8 chip_id;
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bool vddadc_en_ac;
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struct pm2xxx_config config;
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bool ac_conn;
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unsigned int gpio_irq;
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int vbat;
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int old_vbat;
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int failure_case;
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int failure_input_ovv;
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unsigned int lpn_pin;
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struct pm2xxx_interrupts *pm2_int;
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struct regulator *regu;
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struct pm2xxx_bm_data *bat;
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struct mutex lock;
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struct ab8500 *parent;
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struct pm2xxx_charger_info ac;
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struct pm2xxx_charger_platform_data *pdata;
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struct workqueue_struct *charger_wq;
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struct delayed_work check_vbat_work;
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struct work_struct ac_work;
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struct work_struct check_main_thermal_prot_work;
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struct delayed_work check_hw_failure_work;
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struct ux500_charger ac_chg;
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struct power_supply_desc ac_chg_desc;
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struct pm2xxx_charger_event_flags flags;
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};
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#endif /* PM2301_CHARGER_H */
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