mirror of
https://github.com/edk2-porting/linux-next.git
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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
107 lines
3.6 KiB
C
107 lines
3.6 KiB
C
/* timer-regs.h: hardware timer register definitions
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*
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* Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_TIMER_REGS_H
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#define _ASM_TIMER_REGS_H
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#include <asm/sections.h>
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extern unsigned long __nongprelbss __clkin_clock_speed_HZ;
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extern unsigned long __nongprelbss __ext_bus_clock_speed_HZ;
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extern unsigned long __nongprelbss __res_bus_clock_speed_HZ;
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extern unsigned long __nongprelbss __sdram_clock_speed_HZ;
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extern unsigned long __nongprelbss __core_bus_clock_speed_HZ;
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extern unsigned long __nongprelbss __core_clock_speed_HZ;
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extern unsigned long __nongprelbss __dsu_clock_speed_HZ;
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extern unsigned long __nongprelbss __serial_clock_speed_HZ;
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#define __get_CLKC() ({ *(volatile unsigned long *)(0xfeff9a00); })
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static inline void __set_CLKC(unsigned long v)
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{
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int tmp;
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asm volatile(" st%I0.p %2,%M0 \n"
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" setlos %3,%1 \n"
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" membar \n"
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"0: \n"
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" subicc %1,#1,%1,icc0 \n"
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" bnc icc0,#1,0b \n"
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: "=m"(*(volatile unsigned long *) 0xfeff9a00), "=r"(tmp)
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: "r"(v), "i"(256)
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: "icc0");
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}
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#define __get_TCTR() ({ *(volatile unsigned long *)(0xfeff9418); })
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#define __get_TPRV() ({ *(volatile unsigned long *)(0xfeff9420); })
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#define __get_TPRCKSL() ({ *(volatile unsigned long *)(0xfeff9428); })
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#define __get_TCSR(T) ({ *(volatile unsigned long *)(0xfeff9400 + 8 * (T)); })
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#define __get_TxCKSL(T) ({ *(volatile unsigned long *)(0xfeff9430 + 8 * (T)); })
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#define __get_TCSR_DATA(T) ({ __get_TCSR(T) >> 24; })
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#define __set_TCTR(V) do { *(volatile unsigned long *)(0xfeff9418) = (V); mb(); } while(0)
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#define __set_TPRV(V) do { *(volatile unsigned long *)(0xfeff9420) = (V) << 24; mb(); } while(0)
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#define __set_TPRCKSL(V) do { *(volatile unsigned long *)(0xfeff9428) = (V); mb(); } while(0)
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#define __set_TCSR(T,V) \
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do { *(volatile unsigned long *)(0xfeff9400 + 8 * (T)) = (V); mb(); } while(0)
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#define __set_TxCKSL(T,V) \
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do { *(volatile unsigned long *)(0xfeff9430 + 8 * (T)) = (V); mb(); } while(0)
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#define __set_TCSR_DATA(T,V) __set_TCSR(T, (V) << 24)
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#define __set_TxCKSL_DATA(T,V) __set_TxCKSL(T, TxCKSL_EIGHT | __TxCKSL_SELECT((V)))
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/* clock control register */
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#define CLKC_CMODE 0x0f000000
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#define CLKC_SLPL 0x000f0000
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#define CLKC_P0 0x00000100
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#define CLKC_CM 0x00000003
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#define CLKC_CMODE_s 24
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/* timer control register - non-readback mode */
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#define TCTR_MODE_0 0x00000000
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#define TCTR_MODE_2 0x04000000
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#define TCTR_MODE_4 0x08000000
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#define TCTR_MODE_5 0x0a000000
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#define TCTR_RL_LATCH 0x00000000
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#define TCTR_RL_RW_LOW8 0x10000000
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#define TCTR_RL_RW_HIGH8 0x20000000
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#define TCTR_RL_RW_LH8 0x30000000
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#define TCTR_SC_CTR0 0x00000000
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#define TCTR_SC_CTR1 0x40000000
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#define TCTR_SC_CTR2 0x80000000
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/* timer control register - readback mode */
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#define TCTR_CNT0 0x02000000
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#define TCTR_CNT1 0x04000000
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#define TCTR_CNT2 0x08000000
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#define TCTR_NSTATUS 0x10000000
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#define TCTR_NCOUNT 0x20000000
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#define TCTR_SC_READBACK 0xc0000000
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/* timer control status registers - non-readback mode */
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#define TCSRx_DATA 0xff000000
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/* timer control status registers - readback mode */
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#define TCSRx_OUTPUT 0x80000000
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#define TCSRx_NULLCOUNT 0x40000000
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#define TCSRx_RL 0x30000000
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#define TCSRx_MODE 0x07000000
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/* timer clock select registers */
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#define TxCKSL_SELECT 0x0f000000
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#define __TxCKSL_SELECT(X) ((X) << 24)
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#define TxCKSL_EIGHT 0xf0000000
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#endif /* _ASM_TIMER_REGS_H */
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