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edd7eabc85
TPS80031/ TPS80032 Fully Integrated Power Management with Power Path and Battery Charger. The device provides five configurable step-down converters, 11 general purpose LDOs, USB OTG Module, ADC, RTC, 2 PWM, System Voltage Regulator/Battery Charger with Power Path from USB, 32K clock generator. Add the mfd core driver for TPS80031/TPS80032. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviwed-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
638 lines
20 KiB
C
638 lines
20 KiB
C
/*
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* tps80031.h -- TI TPS80031 and TI TPS80032 PMIC driver.
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*
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* Copyright (c) 2012, NVIDIA Corporation.
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*
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* Author: Laxman Dewangan <ldewangan@nvidia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
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* whether express or implied; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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* 02111-1307, USA
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*/
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#ifndef __LINUX_MFD_TPS80031_H
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#define __LINUX_MFD_TPS80031_H
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#include <linux/device.h>
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#include <linux/regmap.h>
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/* Pull-ups/Pull-downs */
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#define TPS80031_CFG_INPUT_PUPD1 0xF0
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#define TPS80031_CFG_INPUT_PUPD2 0xF1
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#define TPS80031_CFG_INPUT_PUPD3 0xF2
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#define TPS80031_CFG_INPUT_PUPD4 0xF3
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#define TPS80031_CFG_LDO_PD1 0xF4
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#define TPS80031_CFG_LDO_PD2 0xF5
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#define TPS80031_CFG_SMPS_PD 0xF6
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/* Real Time Clock */
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#define TPS80031_SECONDS_REG 0x00
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#define TPS80031_MINUTES_REG 0x01
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#define TPS80031_HOURS_REG 0x02
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#define TPS80031_DAYS_REG 0x03
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#define TPS80031_MONTHS_REG 0x04
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#define TPS80031_YEARS_REG 0x05
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#define TPS80031_WEEKS_REG 0x06
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#define TPS80031_ALARM_SECONDS_REG 0x08
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#define TPS80031_ALARM_MINUTES_REG 0x09
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#define TPS80031_ALARM_HOURS_REG 0x0A
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#define TPS80031_ALARM_DAYS_REG 0x0B
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#define TPS80031_ALARM_MONTHS_REG 0x0C
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#define TPS80031_ALARM_YEARS_REG 0x0D
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#define TPS80031_RTC_CTRL_REG 0x10
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#define TPS80031_RTC_STATUS_REG 0x11
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#define TPS80031_RTC_INTERRUPTS_REG 0x12
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#define TPS80031_RTC_COMP_LSB_REG 0x13
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#define TPS80031_RTC_COMP_MSB_REG 0x14
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#define TPS80031_RTC_RESET_STATUS_REG 0x16
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/*PMC Master Module */
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#define TPS80031_PHOENIX_START_CONDITION 0x1F
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#define TPS80031_PHOENIX_MSK_TRANSITION 0x20
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#define TPS80031_STS_HW_CONDITIONS 0x21
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#define TPS80031_PHOENIX_LAST_TURNOFF_STS 0x22
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#define TPS80031_VSYSMIN_LO_THRESHOLD 0x23
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#define TPS80031_VSYSMIN_HI_THRESHOLD 0x24
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#define TPS80031_PHOENIX_DEV_ON 0x25
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#define TPS80031_STS_PWR_GRP_STATE 0x27
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#define TPS80031_PH_CFG_VSYSLOW 0x28
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#define TPS80031_PH_STS_BOOT 0x29
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#define TPS80031_PHOENIX_SENS_TRANSITION 0x2A
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#define TPS80031_PHOENIX_SEQ_CFG 0x2B
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#define TPS80031_PRIMARY_WATCHDOG_CFG 0X2C
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#define TPS80031_KEY_PRESS_DUR_CFG 0X2D
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#define TPS80031_SMPS_LDO_SHORT_STS 0x2E
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/* PMC Slave Module - Broadcast */
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#define TPS80031_BROADCAST_ADDR_ALL 0x31
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#define TPS80031_BROADCAST_ADDR_REF 0x32
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#define TPS80031_BROADCAST_ADDR_PROV 0x33
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#define TPS80031_BROADCAST_ADDR_CLK_RST 0x34
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/* PMC Slave Module SMPS Regulators */
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#define TPS80031_SMPS4_CFG_TRANS 0x41
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#define TPS80031_SMPS4_CFG_STATE 0x42
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#define TPS80031_SMPS4_CFG_VOLTAGE 0x44
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#define TPS80031_VIO_CFG_TRANS 0x47
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#define TPS80031_VIO_CFG_STATE 0x48
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#define TPS80031_VIO_CFG_FORCE 0x49
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#define TPS80031_VIO_CFG_VOLTAGE 0x4A
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#define TPS80031_VIO_CFG_STEP 0x48
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#define TPS80031_SMPS1_CFG_TRANS 0x53
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#define TPS80031_SMPS1_CFG_STATE 0x54
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#define TPS80031_SMPS1_CFG_FORCE 0x55
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#define TPS80031_SMPS1_CFG_VOLTAGE 0x56
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#define TPS80031_SMPS1_CFG_STEP 0x57
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#define TPS80031_SMPS2_CFG_TRANS 0x59
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#define TPS80031_SMPS2_CFG_STATE 0x5A
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#define TPS80031_SMPS2_CFG_FORCE 0x5B
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#define TPS80031_SMPS2_CFG_VOLTAGE 0x5C
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#define TPS80031_SMPS2_CFG_STEP 0x5D
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#define TPS80031_SMPS3_CFG_TRANS 0x65
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#define TPS80031_SMPS3_CFG_STATE 0x66
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#define TPS80031_SMPS3_CFG_VOLTAGE 0x68
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/* PMC Slave Module LDO Regulators */
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#define TPS80031_VANA_CFG_TRANS 0x81
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#define TPS80031_VANA_CFG_STATE 0x82
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#define TPS80031_VANA_CFG_VOLTAGE 0x83
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#define TPS80031_LDO2_CFG_TRANS 0x85
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#define TPS80031_LDO2_CFG_STATE 0x86
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#define TPS80031_LDO2_CFG_VOLTAGE 0x87
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#define TPS80031_LDO4_CFG_TRANS 0x89
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#define TPS80031_LDO4_CFG_STATE 0x8A
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#define TPS80031_LDO4_CFG_VOLTAGE 0x8B
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#define TPS80031_LDO3_CFG_TRANS 0x8D
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#define TPS80031_LDO3_CFG_STATE 0x8E
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#define TPS80031_LDO3_CFG_VOLTAGE 0x8F
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#define TPS80031_LDO6_CFG_TRANS 0x91
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#define TPS80031_LDO6_CFG_STATE 0x92
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#define TPS80031_LDO6_CFG_VOLTAGE 0x93
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#define TPS80031_LDOLN_CFG_TRANS 0x95
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#define TPS80031_LDOLN_CFG_STATE 0x96
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#define TPS80031_LDOLN_CFG_VOLTAGE 0x97
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#define TPS80031_LDO5_CFG_TRANS 0x99
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#define TPS80031_LDO5_CFG_STATE 0x9A
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#define TPS80031_LDO5_CFG_VOLTAGE 0x9B
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#define TPS80031_LDO1_CFG_TRANS 0x9D
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#define TPS80031_LDO1_CFG_STATE 0x9E
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#define TPS80031_LDO1_CFG_VOLTAGE 0x9F
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#define TPS80031_LDOUSB_CFG_TRANS 0xA1
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#define TPS80031_LDOUSB_CFG_STATE 0xA2
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#define TPS80031_LDOUSB_CFG_VOLTAGE 0xA3
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#define TPS80031_LDO7_CFG_TRANS 0xA5
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#define TPS80031_LDO7_CFG_STATE 0xA6
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#define TPS80031_LDO7_CFG_VOLTAGE 0xA7
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/* PMC Slave Module External Control */
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#define TPS80031_REGEN1_CFG_TRANS 0xAE
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#define TPS80031_REGEN1_CFG_STATE 0xAF
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#define TPS80031_REGEN2_CFG_TRANS 0xB1
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#define TPS80031_REGEN2_CFG_STATE 0xB2
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#define TPS80031_SYSEN_CFG_TRANS 0xB4
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#define TPS80031_SYSEN_CFG_STATE 0xB5
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/* PMC Slave Module Internal Control */
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#define TPS80031_NRESPWRON_CFG_TRANS 0xB7
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#define TPS80031_NRESPWRON_CFG_STATE 0xB8
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#define TPS80031_CLK32KAO_CFG_TRANS 0xBA
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#define TPS80031_CLK32KAO_CFG_STATE 0xBB
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#define TPS80031_CLK32KG_CFG_TRANS 0xBD
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#define TPS80031_CLK32KG_CFG_STATE 0xBE
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#define TPS80031_CLK32KAUDIO_CFG_TRANS 0xC0
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#define TPS80031_CLK32KAUDIO_CFG_STATE 0xC1
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#define TPS80031_VRTC_CFG_TRANS 0xC3
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#define TPS80031_VRTC_CFG_STATE 0xC4
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#define TPS80031_BIAS_CFG_TRANS 0xC6
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#define TPS80031_BIAS_CFG_STATE 0xC7
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#define TPS80031_VSYSMIN_HI_CFG_TRANS 0xC9
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#define TPS80031_VSYSMIN_HI_CFG_STATE 0xCA
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#define TPS80031_RC6MHZ_CFG_TRANS 0xCC
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#define TPS80031_RC6MHZ_CFG_STATE 0xCD
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#define TPS80031_TMP_CFG_TRANS 0xCF
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#define TPS80031_TMP_CFG_STATE 0xD0
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/* PMC Slave Module resources assignment */
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#define TPS80031_PREQ1_RES_ASS_A 0xD7
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#define TPS80031_PREQ1_RES_ASS_B 0xD8
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#define TPS80031_PREQ1_RES_ASS_C 0xD9
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#define TPS80031_PREQ2_RES_ASS_A 0xDA
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#define TPS80031_PREQ2_RES_ASS_B 0xDB
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#define TPS80031_PREQ2_RES_ASS_C 0xDC
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#define TPS80031_PREQ3_RES_ASS_A 0xDD
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#define TPS80031_PREQ3_RES_ASS_B 0xDE
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#define TPS80031_PREQ3_RES_ASS_C 0xDF
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/* PMC Slave Module Miscellaneous */
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#define TPS80031_SMPS_OFFSET 0xE0
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#define TPS80031_SMPS_MULT 0xE3
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#define TPS80031_MISC1 0xE4
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#define TPS80031_MISC2 0xE5
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#define TPS80031_BBSPOR_CFG 0xE6
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#define TPS80031_TMP_CFG 0xE7
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/* Battery Charging Controller and Indicator LED */
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#define TPS80031_CONTROLLER_CTRL2 0xDA
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#define TPS80031_CONTROLLER_VSEL_COMP 0xDB
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#define TPS80031_CHARGERUSB_VSYSREG 0xDC
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#define TPS80031_CHARGERUSB_VICHRG_PC 0xDD
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#define TPS80031_LINEAR_CHRG_STS 0xDE
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#define TPS80031_CONTROLLER_INT_MASK 0xE0
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#define TPS80031_CONTROLLER_CTRL1 0xE1
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#define TPS80031_CONTROLLER_WDG 0xE2
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#define TPS80031_CONTROLLER_STAT1 0xE3
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#define TPS80031_CHARGERUSB_INT_STATUS 0xE4
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#define TPS80031_CHARGERUSB_INT_MASK 0xE5
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#define TPS80031_CHARGERUSB_STATUS_INT1 0xE6
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#define TPS80031_CHARGERUSB_STATUS_INT2 0xE7
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#define TPS80031_CHARGERUSB_CTRL1 0xE8
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#define TPS80031_CHARGERUSB_CTRL2 0xE9
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#define TPS80031_CHARGERUSB_CTRL3 0xEA
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#define TPS80031_CHARGERUSB_STAT1 0xEB
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#define TPS80031_CHARGERUSB_VOREG 0xEC
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#define TPS80031_CHARGERUSB_VICHRG 0xED
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#define TPS80031_CHARGERUSB_CINLIMIT 0xEE
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#define TPS80031_CHARGERUSB_CTRLLIMIT1 0xEF
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#define TPS80031_CHARGERUSB_CTRLLIMIT2 0xF0
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#define TPS80031_LED_PWM_CTRL1 0xF4
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#define TPS80031_LED_PWM_CTRL2 0xF5
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/* USB On-The-Go */
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#define TPS80031_BACKUP_REG 0xFA
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#define TPS80031_USB_VENDOR_ID_LSB 0x00
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#define TPS80031_USB_VENDOR_ID_MSB 0x01
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#define TPS80031_USB_PRODUCT_ID_LSB 0x02
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#define TPS80031_USB_PRODUCT_ID_MSB 0x03
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#define TPS80031_USB_VBUS_CTRL_SET 0x04
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#define TPS80031_USB_VBUS_CTRL_CLR 0x05
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#define TPS80031_USB_ID_CTRL_SET 0x06
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#define TPS80031_USB_ID_CTRL_CLR 0x07
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#define TPS80031_USB_VBUS_INT_SRC 0x08
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#define TPS80031_USB_VBUS_INT_LATCH_SET 0x09
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#define TPS80031_USB_VBUS_INT_LATCH_CLR 0x0A
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#define TPS80031_USB_VBUS_INT_EN_LO_SET 0x0B
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#define TPS80031_USB_VBUS_INT_EN_LO_CLR 0x0C
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#define TPS80031_USB_VBUS_INT_EN_HI_SET 0x0D
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#define TPS80031_USB_VBUS_INT_EN_HI_CLR 0x0E
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#define TPS80031_USB_ID_INT_SRC 0x0F
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#define TPS80031_USB_ID_INT_LATCH_SET 0x10
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#define TPS80031_USB_ID_INT_LATCH_CLR 0x11
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#define TPS80031_USB_ID_INT_EN_LO_SET 0x12
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#define TPS80031_USB_ID_INT_EN_LO_CLR 0x13
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#define TPS80031_USB_ID_INT_EN_HI_SET 0x14
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#define TPS80031_USB_ID_INT_EN_HI_CLR 0x15
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#define TPS80031_USB_OTG_ADP_CTRL 0x16
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#define TPS80031_USB_OTG_ADP_HIGH 0x17
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#define TPS80031_USB_OTG_ADP_LOW 0x18
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#define TPS80031_USB_OTG_ADP_RISE 0x19
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#define TPS80031_USB_OTG_REVISION 0x1A
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/* Gas Gauge */
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#define TPS80031_FG_REG_00 0xC0
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#define TPS80031_FG_REG_01 0xC1
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#define TPS80031_FG_REG_02 0xC2
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#define TPS80031_FG_REG_03 0xC3
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#define TPS80031_FG_REG_04 0xC4
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#define TPS80031_FG_REG_05 0xC5
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#define TPS80031_FG_REG_06 0xC6
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#define TPS80031_FG_REG_07 0xC7
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#define TPS80031_FG_REG_08 0xC8
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#define TPS80031_FG_REG_09 0xC9
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#define TPS80031_FG_REG_10 0xCA
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#define TPS80031_FG_REG_11 0xCB
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/* General Purpose ADC */
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#define TPS80031_GPADC_CTRL 0x2E
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#define TPS80031_GPADC_CTRL2 0x2F
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#define TPS80031_RTSELECT_LSB 0x32
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#define TPS80031_RTSELECT_ISB 0x33
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#define TPS80031_RTSELECT_MSB 0x34
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#define TPS80031_GPSELECT_ISB 0x35
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#define TPS80031_CTRL_P1 0x36
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#define TPS80031_RTCH0_LSB 0x37
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#define TPS80031_RTCH0_MSB 0x38
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#define TPS80031_RTCH1_LSB 0x39
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#define TPS80031_RTCH1_MSB 0x3A
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#define TPS80031_GPCH0_LSB 0x3B
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#define TPS80031_GPCH0_MSB 0x3C
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/* SIM, MMC and Battery Detection */
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#define TPS80031_SIMDEBOUNCING 0xEB
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#define TPS80031_SIMCTRL 0xEC
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#define TPS80031_MMCDEBOUNCING 0xED
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#define TPS80031_MMCCTRL 0xEE
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#define TPS80031_BATDEBOUNCING 0xEF
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/* Vibrator Driver and PWMs */
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#define TPS80031_VIBCTRL 0x9B
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#define TPS80031_VIBMODE 0x9C
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#define TPS80031_PWM1ON 0xBA
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#define TPS80031_PWM1OFF 0xBB
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#define TPS80031_PWM2ON 0xBD
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#define TPS80031_PWM2OFF 0xBE
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/* Control Interface */
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#define TPS80031_INT_STS_A 0xD0
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#define TPS80031_INT_STS_B 0xD1
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#define TPS80031_INT_STS_C 0xD2
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#define TPS80031_INT_MSK_LINE_A 0xD3
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#define TPS80031_INT_MSK_LINE_B 0xD4
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#define TPS80031_INT_MSK_LINE_C 0xD5
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#define TPS80031_INT_MSK_STS_A 0xD6
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#define TPS80031_INT_MSK_STS_B 0xD7
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#define TPS80031_INT_MSK_STS_C 0xD8
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#define TPS80031_TOGGLE1 0x90
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#define TPS80031_TOGGLE2 0x91
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#define TPS80031_TOGGLE3 0x92
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#define TPS80031_PWDNSTATUS1 0x93
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#define TPS80031_PWDNSTATUS2 0x94
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#define TPS80031_VALIDITY0 0x17
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#define TPS80031_VALIDITY1 0x18
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#define TPS80031_VALIDITY2 0x19
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#define TPS80031_VALIDITY3 0x1A
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#define TPS80031_VALIDITY4 0x1B
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#define TPS80031_VALIDITY5 0x1C
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#define TPS80031_VALIDITY6 0x1D
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#define TPS80031_VALIDITY7 0x1E
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/* Version number related register */
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#define TPS80031_JTAGVERNUM 0x87
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#define TPS80031_EPROM_REV 0xDF
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/* GPADC Trimming Bits. */
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#define TPS80031_GPADC_TRIM0 0xCC
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#define TPS80031_GPADC_TRIM1 0xCD
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#define TPS80031_GPADC_TRIM2 0xCE
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#define TPS80031_GPADC_TRIM3 0xCF
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#define TPS80031_GPADC_TRIM4 0xD0
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#define TPS80031_GPADC_TRIM5 0xD1
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#define TPS80031_GPADC_TRIM6 0xD2
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#define TPS80031_GPADC_TRIM7 0xD3
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#define TPS80031_GPADC_TRIM8 0xD4
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#define TPS80031_GPADC_TRIM9 0xD5
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#define TPS80031_GPADC_TRIM10 0xD6
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#define TPS80031_GPADC_TRIM11 0xD7
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#define TPS80031_GPADC_TRIM12 0xD8
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#define TPS80031_GPADC_TRIM13 0xD9
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#define TPS80031_GPADC_TRIM14 0xDA
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#define TPS80031_GPADC_TRIM15 0xDB
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#define TPS80031_GPADC_TRIM16 0xDC
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#define TPS80031_GPADC_TRIM17 0xDD
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#define TPS80031_GPADC_TRIM18 0xDE
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/* TPS80031_CONTROLLER_STAT1 bit fields */
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#define TPS80031_CONTROLLER_STAT1_BAT_TEMP 0
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#define TPS80031_CONTROLLER_STAT1_BAT_REMOVED 1
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#define TPS80031_CONTROLLER_STAT1_VBUS_DET 2
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#define TPS80031_CONTROLLER_STAT1_VAC_DET 3
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#define TPS80031_CONTROLLER_STAT1_FAULT_WDG 4
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#define TPS80031_CONTROLLER_STAT1_LINCH_GATED 6
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/* TPS80031_CONTROLLER_INT_MASK bit filed */
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#define TPS80031_CONTROLLER_INT_MASK_MVAC_DET 0
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#define TPS80031_CONTROLLER_INT_MASK_MVBUS_DET 1
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#define TPS80031_CONTROLLER_INT_MASK_MBAT_TEMP 2
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#define TPS80031_CONTROLLER_INT_MASK_MFAULT_WDG 3
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#define TPS80031_CONTROLLER_INT_MASK_MBAT_REMOVED 4
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#define TPS80031_CONTROLLER_INT_MASK_MLINCH_GATED 5
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#define TPS80031_CHARGE_CONTROL_SUB_INT_MASK 0x3F
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/* TPS80031_PHOENIX_DEV_ON bit field */
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#define TPS80031_DEVOFF 0x1
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#define TPS80031_EXT_CONTROL_CFG_TRANS 0
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#define TPS80031_EXT_CONTROL_CFG_STATE 1
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/* State register field */
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#define TPS80031_STATE_OFF 0x00
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#define TPS80031_STATE_ON 0x01
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#define TPS80031_STATE_MASK 0x03
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/* Trans register field */
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#define TPS80031_TRANS_ACTIVE_OFF 0x00
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#define TPS80031_TRANS_ACTIVE_ON 0x01
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#define TPS80031_TRANS_ACTIVE_MASK 0x03
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#define TPS80031_TRANS_SLEEP_OFF 0x00
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#define TPS80031_TRANS_SLEEP_ON 0x04
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#define TPS80031_TRANS_SLEEP_MASK 0x0C
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#define TPS80031_TRANS_OFF_OFF 0x00
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#define TPS80031_TRANS_OFF_ACTIVE 0x10
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#define TPS80031_TRANS_OFF_MASK 0x30
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#define TPS80031_EXT_PWR_REQ (TPS80031_PWR_REQ_INPUT_PREQ1 | \
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TPS80031_PWR_REQ_INPUT_PREQ2 | \
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TPS80031_PWR_REQ_INPUT_PREQ3)
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/* TPS80031_BBSPOR_CFG bit field */
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#define TPS80031_BBSPOR_CHG_EN 0x8
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#define TPS80031_MAX_REGISTER 0xFF
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struct i2c_client;
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/* Supported chips */
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enum chips {
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TPS80031 = 0x00000001,
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TPS80032 = 0x00000002,
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};
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enum {
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TPS80031_INT_PWRON,
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TPS80031_INT_RPWRON,
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TPS80031_INT_SYS_VLOW,
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TPS80031_INT_RTC_ALARM,
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TPS80031_INT_RTC_PERIOD,
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TPS80031_INT_HOT_DIE,
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TPS80031_INT_VXX_SHORT,
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TPS80031_INT_SPDURATION,
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TPS80031_INT_WATCHDOG,
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TPS80031_INT_BAT,
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TPS80031_INT_SIM,
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TPS80031_INT_MMC,
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TPS80031_INT_RES,
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TPS80031_INT_GPADC_RT,
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TPS80031_INT_GPADC_SW2_EOC,
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TPS80031_INT_CC_AUTOCAL,
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TPS80031_INT_ID_WKUP,
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TPS80031_INT_VBUSS_WKUP,
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TPS80031_INT_ID,
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TPS80031_INT_VBUS,
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TPS80031_INT_CHRG_CTRL,
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TPS80031_INT_EXT_CHRG,
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TPS80031_INT_INT_CHRG,
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TPS80031_INT_RES2,
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TPS80031_INT_BAT_TEMP_OVRANGE,
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TPS80031_INT_BAT_REMOVED,
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TPS80031_INT_VBUS_DET,
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TPS80031_INT_VAC_DET,
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TPS80031_INT_FAULT_WDG,
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TPS80031_INT_LINCH_GATED,
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/* Last interrupt id to get the end number */
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TPS80031_INT_NR,
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};
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/* TPS80031 Slave IDs */
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#define TPS80031_NUM_SLAVES 4
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#define TPS80031_SLAVE_ID0 0
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#define TPS80031_SLAVE_ID1 1
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#define TPS80031_SLAVE_ID2 2
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#define TPS80031_SLAVE_ID3 3
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|
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/* TPS80031 I2C addresses */
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#define TPS80031_I2C_ID0_ADDR 0x12
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#define TPS80031_I2C_ID1_ADDR 0x48
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#define TPS80031_I2C_ID2_ADDR 0x49
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#define TPS80031_I2C_ID3_ADDR 0x4A
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enum {
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TPS80031_REGULATOR_VIO,
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TPS80031_REGULATOR_SMPS1,
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TPS80031_REGULATOR_SMPS2,
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TPS80031_REGULATOR_SMPS3,
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TPS80031_REGULATOR_SMPS4,
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TPS80031_REGULATOR_VANA,
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TPS80031_REGULATOR_LDO1,
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TPS80031_REGULATOR_LDO2,
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TPS80031_REGULATOR_LDO3,
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TPS80031_REGULATOR_LDO4,
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TPS80031_REGULATOR_LDO5,
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TPS80031_REGULATOR_LDO6,
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TPS80031_REGULATOR_LDO7,
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TPS80031_REGULATOR_LDOLN,
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TPS80031_REGULATOR_LDOUSB,
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TPS80031_REGULATOR_VBUS,
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TPS80031_REGULATOR_REGEN1,
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TPS80031_REGULATOR_REGEN2,
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TPS80031_REGULATOR_SYSEN,
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TPS80031_REGULATOR_MAX,
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|
};
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|
|
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/* Different configurations for the rails */
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|
enum {
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|
/* USBLDO input selection */
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|
TPS80031_USBLDO_INPUT_VSYS = 0x00000001,
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|
TPS80031_USBLDO_INPUT_PMID = 0x00000002,
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|
|
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/* LDO3 output mode */
|
|
TPS80031_LDO3_OUTPUT_VIB = 0x00000004,
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|
|
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/* VBUS configuration */
|
|
TPS80031_VBUS_DISCHRG_EN_PDN = 0x00000004,
|
|
TPS80031_VBUS_SW_ONLY = 0x00000008,
|
|
TPS80031_VBUS_SW_N_ID = 0x00000010,
|
|
};
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|
|
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/* External controls requests */
|
|
enum tps80031_ext_control {
|
|
TPS80031_PWR_REQ_INPUT_NONE = 0x00000000,
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|
TPS80031_PWR_REQ_INPUT_PREQ1 = 0x00000001,
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|
TPS80031_PWR_REQ_INPUT_PREQ2 = 0x00000002,
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|
TPS80031_PWR_REQ_INPUT_PREQ3 = 0x00000004,
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|
TPS80031_PWR_OFF_ON_SLEEP = 0x00000008,
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|
TPS80031_PWR_ON_ON_SLEEP = 0x00000010,
|
|
};
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|
|
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enum tps80031_pupd_pins {
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|
TPS80031_PREQ1 = 0,
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TPS80031_PREQ2A,
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TPS80031_PREQ2B,
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TPS80031_PREQ2C,
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|
TPS80031_PREQ3,
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|
TPS80031_NRES_WARM,
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|
TPS80031_PWM_FORCE,
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|
TPS80031_CHRG_EXT_CHRG_STATZ,
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|
TPS80031_SIM,
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|
TPS80031_MMC,
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|
TPS80031_GPADC_START,
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|
TPS80031_DVSI2C_SCL,
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|
TPS80031_DVSI2C_SDA,
|
|
TPS80031_CTLI2C_SCL,
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|
TPS80031_CTLI2C_SDA,
|
|
};
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|
|
|
enum tps80031_pupd_settings {
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|
TPS80031_PUPD_NORMAL,
|
|
TPS80031_PUPD_PULLDOWN,
|
|
TPS80031_PUPD_PULLUP,
|
|
};
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|
|
|
struct tps80031 {
|
|
struct device *dev;
|
|
unsigned long chip_info;
|
|
int es_version;
|
|
struct i2c_client *clients[TPS80031_NUM_SLAVES];
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|
struct regmap *regmap[TPS80031_NUM_SLAVES];
|
|
struct regmap_irq_chip_data *irq_data;
|
|
};
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|
|
|
struct tps80031_pupd_init_data {
|
|
int input_pin;
|
|
int setting;
|
|
};
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|
|
|
/*
|
|
* struct tps80031_regulator_platform_data - tps80031 regulator platform data.
|
|
*
|
|
* @reg_init_data: The regulator init data.
|
|
* @ext_ctrl_flag: External control flag for sleep/power request control.
|
|
* @config_flags: Configuration flag to configure the rails.
|
|
* It should be ORed of config enums.
|
|
*/
|
|
|
|
struct tps80031_regulator_platform_data {
|
|
struct regulator_init_data *reg_init_data;
|
|
unsigned int ext_ctrl_flag;
|
|
unsigned int config_flags;
|
|
};
|
|
|
|
struct tps80031_platform_data {
|
|
int irq_base;
|
|
bool use_power_off;
|
|
struct tps80031_pupd_init_data *pupd_init_data;
|
|
int pupd_init_data_size;
|
|
struct tps80031_regulator_platform_data
|
|
*regulator_pdata[TPS80031_REGULATOR_MAX];
|
|
};
|
|
|
|
static inline int tps80031_write(struct device *dev, int sid,
|
|
int reg, uint8_t val)
|
|
{
|
|
struct tps80031 *tps80031 = dev_get_drvdata(dev);
|
|
|
|
return regmap_write(tps80031->regmap[sid], reg, val);
|
|
}
|
|
|
|
static inline int tps80031_writes(struct device *dev, int sid, int reg,
|
|
int len, uint8_t *val)
|
|
{
|
|
struct tps80031 *tps80031 = dev_get_drvdata(dev);
|
|
|
|
return regmap_bulk_write(tps80031->regmap[sid], reg, val, len);
|
|
}
|
|
|
|
static inline int tps80031_read(struct device *dev, int sid,
|
|
int reg, uint8_t *val)
|
|
{
|
|
struct tps80031 *tps80031 = dev_get_drvdata(dev);
|
|
unsigned int ival;
|
|
int ret;
|
|
|
|
ret = regmap_read(tps80031->regmap[sid], reg, &ival);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed reading from reg 0x%02x\n", reg);
|
|
return ret;
|
|
}
|
|
|
|
*val = ival;
|
|
return ret;
|
|
}
|
|
|
|
static inline int tps80031_reads(struct device *dev, int sid,
|
|
int reg, int len, uint8_t *val)
|
|
{
|
|
struct tps80031 *tps80031 = dev_get_drvdata(dev);
|
|
|
|
return regmap_bulk_read(tps80031->regmap[sid], reg, val, len);
|
|
}
|
|
|
|
static inline int tps80031_set_bits(struct device *dev, int sid,
|
|
int reg, uint8_t bit_mask)
|
|
{
|
|
struct tps80031 *tps80031 = dev_get_drvdata(dev);
|
|
|
|
return regmap_update_bits(tps80031->regmap[sid], reg,
|
|
bit_mask, bit_mask);
|
|
}
|
|
|
|
static inline int tps80031_clr_bits(struct device *dev, int sid,
|
|
int reg, uint8_t bit_mask)
|
|
{
|
|
struct tps80031 *tps80031 = dev_get_drvdata(dev);
|
|
|
|
return regmap_update_bits(tps80031->regmap[sid], reg, bit_mask, 0);
|
|
}
|
|
|
|
static inline int tps80031_update(struct device *dev, int sid,
|
|
int reg, uint8_t val, uint8_t mask)
|
|
{
|
|
struct tps80031 *tps80031 = dev_get_drvdata(dev);
|
|
|
|
return regmap_update_bits(tps80031->regmap[sid], reg, mask, val);
|
|
}
|
|
|
|
static inline unsigned long tps80031_get_chip_info(struct device *dev)
|
|
{
|
|
struct tps80031 *tps80031 = dev_get_drvdata(dev);
|
|
|
|
return tps80031->chip_info;
|
|
}
|
|
|
|
static inline int tps80031_get_pmu_version(struct device *dev)
|
|
{
|
|
struct tps80031 *tps80031 = dev_get_drvdata(dev);
|
|
|
|
return tps80031->es_version;
|
|
}
|
|
|
|
static inline int tps80031_irq_get_virq(struct device *dev, int irq)
|
|
{
|
|
struct tps80031 *tps80031 = dev_get_drvdata(dev);
|
|
|
|
return regmap_irq_get_virq(tps80031->irq_data, irq);
|
|
}
|
|
|
|
extern int tps80031_ext_power_req_config(struct device *dev,
|
|
unsigned long ext_ctrl_flag, int preq_bit,
|
|
int state_reg_add, int trans_reg_add);
|
|
#endif /*__LINUX_MFD_TPS80031_H */
|