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https://github.com/edk2-porting/linux-next.git
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0d811cda22
'HSUSB_CTRL_DPSEHV_CLAMP' in 'val' is duplicated. Signed-off-by: Zhang Yunkai <zhang.yunkai@zte.com.cn> Link: https://lore.kernel.org/r/20210319113612.494623-1-zhang.yunkai@zte.com.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
571 lines
15 KiB
C
571 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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/* USB QSCRATCH Hardware registers */
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#define QSCRATCH_GENERAL_CFG (0x08)
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#define HSUSB_PHY_CTRL_REG (0x10)
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/* PHY_CTRL_REG */
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#define HSUSB_CTRL_DMSEHV_CLAMP BIT(24)
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#define HSUSB_CTRL_USB2_SUSPEND BIT(23)
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#define HSUSB_CTRL_UTMI_CLK_EN BIT(21)
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#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20)
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#define HSUSB_CTRL_USE_CLKCORE BIT(18)
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#define HSUSB_CTRL_DPSEHV_CLAMP BIT(17)
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#define HSUSB_CTRL_COMMONONN BIT(11)
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#define HSUSB_CTRL_ID_HV_CLAMP BIT(9)
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#define HSUSB_CTRL_OTGSESSVLD_CLAMP BIT(8)
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#define HSUSB_CTRL_CLAMP_EN BIT(7)
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#define HSUSB_CTRL_RETENABLEN BIT(1)
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#define HSUSB_CTRL_POR BIT(0)
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/* QSCRATCH_GENERAL_CFG */
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#define HSUSB_GCFG_XHCI_REV BIT(2)
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/* USB QSCRATCH Hardware registers */
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#define SSUSB_PHY_CTRL_REG (0x00)
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#define SSUSB_PHY_PARAM_CTRL_1 (0x04)
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#define SSUSB_PHY_PARAM_CTRL_2 (0x08)
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#define CR_PROTOCOL_DATA_IN_REG (0x0c)
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#define CR_PROTOCOL_DATA_OUT_REG (0x10)
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#define CR_PROTOCOL_CAP_ADDR_REG (0x14)
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#define CR_PROTOCOL_CAP_DATA_REG (0x18)
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#define CR_PROTOCOL_READ_REG (0x1c)
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#define CR_PROTOCOL_WRITE_REG (0x20)
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/* PHY_CTRL_REG */
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#define SSUSB_CTRL_REF_USE_PAD BIT(28)
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#define SSUSB_CTRL_TEST_POWERDOWN BIT(27)
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#define SSUSB_CTRL_LANE0_PWR_PRESENT BIT(24)
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#define SSUSB_CTRL_SS_PHY_EN BIT(8)
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#define SSUSB_CTRL_SS_PHY_RESET BIT(7)
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/* SSPHY control registers - Does this need 0x30? */
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#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * (lane))
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#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane) (0x1002 + 0x100 * (lane))
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/* SSPHY SoC version specific values */
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#define SSPHY_RX_EQ_VALUE 4 /* Override value for rx_eq */
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/* Override value for transmit preemphasis */
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#define SSPHY_TX_DEEMPH_3_5DB 23
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/* Override value for mpll */
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#define SSPHY_MPLL_VALUE 0
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/* QSCRATCH PHY_PARAM_CTRL1 fields */
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#define PHY_PARAM_CTRL1_TX_FULL_SWING_MASK GENMASK(26, 19)
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#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK GENMASK(19, 13)
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#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK GENMASK(13, 7)
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#define PHY_PARAM_CTRL1_LOS_BIAS_MASK GENMASK(7, 2)
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#define PHY_PARAM_CTRL1_MASK \
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(PHY_PARAM_CTRL1_TX_FULL_SWING_MASK | \
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PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK | \
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PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK | \
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PHY_PARAM_CTRL1_LOS_BIAS_MASK)
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#define PHY_PARAM_CTRL1_TX_FULL_SWING(x) \
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(((x) << 20) & PHY_PARAM_CTRL1_TX_FULL_SWING_MASK)
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#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB(x) \
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(((x) << 14) & PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK)
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#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(x) \
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(((x) << 8) & PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK)
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#define PHY_PARAM_CTRL1_LOS_BIAS(x) \
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(((x) << 3) & PHY_PARAM_CTRL1_LOS_BIAS_MASK)
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/* RX OVRD IN HI bits */
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#define RX_OVRD_IN_HI_RX_RESET_OVRD BIT(13)
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#define RX_OVRD_IN_HI_RX_RX_RESET BIT(12)
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#define RX_OVRD_IN_HI_RX_EQ_OVRD BIT(11)
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#define RX_OVRD_IN_HI_RX_EQ_MASK GENMASK(10, 7)
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#define RX_OVRD_IN_HI_RX_EQ(x) ((x) << 8)
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#define RX_OVRD_IN_HI_RX_EQ_EN_OVRD BIT(7)
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#define RX_OVRD_IN_HI_RX_EQ_EN BIT(6)
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#define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD BIT(5)
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#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK GENMASK(4, 2)
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#define RX_OVRD_IN_HI_RX_RATE_OVRD BIT(2)
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#define RX_OVRD_IN_HI_RX_RATE_MASK GENMASK(2, 0)
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/* TX OVRD DRV LO register bits */
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#define TX_OVRD_DRV_LO_AMPLITUDE_MASK GENMASK(6, 0)
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#define TX_OVRD_DRV_LO_PREEMPH_MASK GENMASK(13, 6)
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#define TX_OVRD_DRV_LO_PREEMPH(x) ((x) << 7)
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#define TX_OVRD_DRV_LO_EN BIT(14)
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/* MPLL bits */
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#define SSPHY_MPLL_MASK GENMASK(8, 5)
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#define SSPHY_MPLL(x) ((x) << 5)
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/* SS CAP register bits */
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#define SS_CR_CAP_ADDR_REG BIT(0)
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#define SS_CR_CAP_DATA_REG BIT(0)
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#define SS_CR_READ_REG BIT(0)
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#define SS_CR_WRITE_REG BIT(0)
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struct usb_phy {
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void __iomem *base;
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struct device *dev;
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struct clk *xo_clk;
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struct clk *ref_clk;
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u32 rx_eq;
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u32 tx_deamp_3_5db;
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u32 mpll;
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};
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struct phy_drvdata {
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struct phy_ops ops;
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u32 clk_rate;
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};
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/**
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* Write register and read back masked value to confirm it is written
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*
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* @base - QCOM DWC3 PHY base virtual address.
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* @offset - register offset.
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* @mask - register bitmask specifying what should be updated
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* @val - value to write.
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*/
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static inline void usb_phy_write_readback(struct usb_phy *phy_dwc3,
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u32 offset,
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const u32 mask, u32 val)
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{
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u32 write_val, tmp = readl(phy_dwc3->base + offset);
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tmp &= ~mask; /* retain other bits */
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write_val = tmp | val;
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writel(write_val, phy_dwc3->base + offset);
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/* Read back to see if val was written */
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tmp = readl(phy_dwc3->base + offset);
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tmp &= mask; /* clear other bits */
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if (tmp != val)
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dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n", val, offset);
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}
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static int wait_for_latch(void __iomem *addr)
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{
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u32 retry = 10;
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while (true) {
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if (!readl(addr))
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break;
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if (--retry == 0)
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return -ETIMEDOUT;
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usleep_range(10, 20);
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}
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return 0;
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}
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/**
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* Write SSPHY register
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*
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* @base - QCOM DWC3 PHY base virtual address.
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* @addr - SSPHY address to write.
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* @val - value to write.
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*/
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static int usb_ss_write_phycreg(struct usb_phy *phy_dwc3,
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u32 addr, u32 val)
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{
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int ret;
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writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
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writel(SS_CR_CAP_ADDR_REG,
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phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
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ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
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if (ret)
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goto err_wait;
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writel(val, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
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writel(SS_CR_CAP_DATA_REG,
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phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
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ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
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if (ret)
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goto err_wait;
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writel(SS_CR_WRITE_REG, phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
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ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
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err_wait:
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if (ret)
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dev_err(phy_dwc3->dev, "timeout waiting for latch\n");
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return ret;
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}
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/**
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* Read SSPHY register.
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*
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* @base - QCOM DWC3 PHY base virtual address.
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* @addr - SSPHY address to read.
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*/
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static int usb_ss_read_phycreg(struct usb_phy *phy_dwc3,
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u32 addr, u32 *val)
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{
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int ret;
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writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
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writel(SS_CR_CAP_ADDR_REG,
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phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
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ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
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if (ret)
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goto err_wait;
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/*
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* Due to hardware bug, first read of SSPHY register might be
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* incorrect. Hence as workaround, SW should perform SSPHY register
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* read twice, but use only second read and ignore first read.
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*/
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writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
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ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
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if (ret)
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goto err_wait;
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/* throwaway read */
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readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
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writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
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ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
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if (ret)
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goto err_wait;
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*val = readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
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err_wait:
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return ret;
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}
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static int qcom_ipq806x_usb_hs_phy_init(struct phy *phy)
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{
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struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
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int ret;
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u32 val;
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ret = clk_prepare_enable(phy_dwc3->xo_clk);
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if (ret)
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return ret;
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ret = clk_prepare_enable(phy_dwc3->ref_clk);
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if (ret) {
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clk_disable_unprepare(phy_dwc3->xo_clk);
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return ret;
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}
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/*
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* HSPHY Initialization: Enable UTMI clock, select 19.2MHz fsel
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* enable clamping, and disable RETENTION (power-on default is ENABLED)
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*/
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val = HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_DMSEHV_CLAMP |
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HSUSB_CTRL_RETENABLEN | HSUSB_CTRL_COMMONONN |
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HSUSB_CTRL_OTGSESSVLD_CLAMP | HSUSB_CTRL_ID_HV_CLAMP |
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HSUSB_CTRL_UTMI_OTG_VBUS_VALID | HSUSB_CTRL_UTMI_CLK_EN |
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HSUSB_CTRL_CLAMP_EN | 0x70;
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/* use core clock if external reference is not present */
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if (!phy_dwc3->xo_clk)
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val |= HSUSB_CTRL_USE_CLKCORE;
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writel(val, phy_dwc3->base + HSUSB_PHY_CTRL_REG);
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usleep_range(2000, 2200);
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/* Disable (bypass) VBUS and ID filters */
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writel(HSUSB_GCFG_XHCI_REV, phy_dwc3->base + QSCRATCH_GENERAL_CFG);
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return 0;
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}
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static int qcom_ipq806x_usb_hs_phy_exit(struct phy *phy)
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{
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struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
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clk_disable_unprepare(phy_dwc3->ref_clk);
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clk_disable_unprepare(phy_dwc3->xo_clk);
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return 0;
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}
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static int qcom_ipq806x_usb_ss_phy_init(struct phy *phy)
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{
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struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
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int ret;
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u32 data;
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ret = clk_prepare_enable(phy_dwc3->xo_clk);
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if (ret)
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return ret;
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ret = clk_prepare_enable(phy_dwc3->ref_clk);
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if (ret) {
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clk_disable_unprepare(phy_dwc3->xo_clk);
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return ret;
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}
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/* reset phy */
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data = readl(phy_dwc3->base + SSUSB_PHY_CTRL_REG);
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writel(data | SSUSB_CTRL_SS_PHY_RESET,
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phy_dwc3->base + SSUSB_PHY_CTRL_REG);
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usleep_range(2000, 2200);
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writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
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/* clear REF_PAD if we don't have XO clk */
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if (!phy_dwc3->xo_clk)
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data &= ~SSUSB_CTRL_REF_USE_PAD;
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else
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data |= SSUSB_CTRL_REF_USE_PAD;
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writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
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/* wait for ref clk to become stable, this can take up to 30ms */
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msleep(30);
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data |= SSUSB_CTRL_SS_PHY_EN | SSUSB_CTRL_LANE0_PWR_PRESENT;
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writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
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/*
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* WORKAROUND: There is SSPHY suspend bug due to which USB enumerates
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* in HS mode instead of SS mode. Workaround it by asserting
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* LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode
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*/
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ret = usb_ss_read_phycreg(phy_dwc3, 0x102D, &data);
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if (ret)
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goto err_phy_trans;
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data |= (1 << 7);
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ret = usb_ss_write_phycreg(phy_dwc3, 0x102D, data);
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if (ret)
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goto err_phy_trans;
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ret = usb_ss_read_phycreg(phy_dwc3, 0x1010, &data);
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if (ret)
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goto err_phy_trans;
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data &= ~0xff0;
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data |= 0x20;
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ret = usb_ss_write_phycreg(phy_dwc3, 0x1010, data);
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if (ret)
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goto err_phy_trans;
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/*
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* Fix RX Equalization setting as follows
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* LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
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* LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
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* LANE0.RX_OVRD_IN_HI.RX_EQ set based on SoC version
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* LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
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*/
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ret = usb_ss_read_phycreg(phy_dwc3, SSPHY_CTRL_RX_OVRD_IN_HI(0), &data);
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if (ret)
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goto err_phy_trans;
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data &= ~RX_OVRD_IN_HI_RX_EQ_EN;
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data |= RX_OVRD_IN_HI_RX_EQ_EN_OVRD;
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data &= ~RX_OVRD_IN_HI_RX_EQ_MASK;
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data |= RX_OVRD_IN_HI_RX_EQ(phy_dwc3->rx_eq);
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data |= RX_OVRD_IN_HI_RX_EQ_OVRD;
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ret = usb_ss_write_phycreg(phy_dwc3,
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SSPHY_CTRL_RX_OVRD_IN_HI(0), data);
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if (ret)
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goto err_phy_trans;
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/*
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* Set EQ and TX launch amplitudes as follows
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* LANE0.TX_OVRD_DRV_LO.PREEMPH set based on SoC version
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* LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 110
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* LANE0.TX_OVRD_DRV_LO.EN set to 1.
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*/
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ret = usb_ss_read_phycreg(phy_dwc3,
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SSPHY_CTRL_TX_OVRD_DRV_LO(0), &data);
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if (ret)
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goto err_phy_trans;
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data &= ~TX_OVRD_DRV_LO_PREEMPH_MASK;
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data |= TX_OVRD_DRV_LO_PREEMPH(phy_dwc3->tx_deamp_3_5db);
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data &= ~TX_OVRD_DRV_LO_AMPLITUDE_MASK;
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data |= 0x6E;
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data |= TX_OVRD_DRV_LO_EN;
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ret = usb_ss_write_phycreg(phy_dwc3,
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SSPHY_CTRL_TX_OVRD_DRV_LO(0), data);
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if (ret)
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goto err_phy_trans;
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data = 0;
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data &= ~SSPHY_MPLL_MASK;
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data |= SSPHY_MPLL(phy_dwc3->mpll);
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usb_ss_write_phycreg(phy_dwc3, 0x30, data);
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/*
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* Set the QSCRATCH PHY_PARAM_CTRL1 parameters as follows
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* TX_FULL_SWING [26:20] amplitude to 110
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* TX_DEEMPH_6DB [19:14] to 32
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* TX_DEEMPH_3_5DB [13:8] set based on SoC version
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* LOS_BIAS [7:3] to 9
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*/
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data = readl(phy_dwc3->base + SSUSB_PHY_PARAM_CTRL_1);
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data &= ~PHY_PARAM_CTRL1_MASK;
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data |= PHY_PARAM_CTRL1_TX_FULL_SWING(0x6e) |
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PHY_PARAM_CTRL1_TX_DEEMPH_6DB(0x20) |
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PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(phy_dwc3->tx_deamp_3_5db) |
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PHY_PARAM_CTRL1_LOS_BIAS(0x9);
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usb_phy_write_readback(phy_dwc3, SSUSB_PHY_PARAM_CTRL_1,
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PHY_PARAM_CTRL1_MASK, data);
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err_phy_trans:
|
|
return ret;
|
|
}
|
|
|
|
static int qcom_ipq806x_usb_ss_phy_exit(struct phy *phy)
|
|
{
|
|
struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
|
|
|
|
/* Sequence to put SSPHY in low power state:
|
|
* 1. Clear REF_PHY_EN in PHY_CTRL_REG
|
|
* 2. Clear REF_USE_PAD in PHY_CTRL_REG
|
|
* 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention
|
|
*/
|
|
usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
|
|
SSUSB_CTRL_SS_PHY_EN, 0x0);
|
|
usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
|
|
SSUSB_CTRL_REF_USE_PAD, 0x0);
|
|
usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
|
|
SSUSB_CTRL_TEST_POWERDOWN, 0x0);
|
|
|
|
clk_disable_unprepare(phy_dwc3->ref_clk);
|
|
clk_disable_unprepare(phy_dwc3->xo_clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct phy_drvdata qcom_ipq806x_usb_hs_drvdata = {
|
|
.ops = {
|
|
.init = qcom_ipq806x_usb_hs_phy_init,
|
|
.exit = qcom_ipq806x_usb_hs_phy_exit,
|
|
.owner = THIS_MODULE,
|
|
},
|
|
.clk_rate = 60000000,
|
|
};
|
|
|
|
static const struct phy_drvdata qcom_ipq806x_usb_ss_drvdata = {
|
|
.ops = {
|
|
.init = qcom_ipq806x_usb_ss_phy_init,
|
|
.exit = qcom_ipq806x_usb_ss_phy_exit,
|
|
.owner = THIS_MODULE,
|
|
},
|
|
.clk_rate = 125000000,
|
|
};
|
|
|
|
static const struct of_device_id qcom_ipq806x_usb_phy_table[] = {
|
|
{ .compatible = "qcom,ipq806x-usb-phy-hs",
|
|
.data = &qcom_ipq806x_usb_hs_drvdata },
|
|
{ .compatible = "qcom,ipq806x-usb-phy-ss",
|
|
.data = &qcom_ipq806x_usb_ss_drvdata },
|
|
{ /* Sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, qcom_ipq806x_usb_phy_table);
|
|
|
|
static int qcom_ipq806x_usb_phy_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *res;
|
|
resource_size_t size;
|
|
struct phy *generic_phy;
|
|
struct usb_phy *phy_dwc3;
|
|
const struct phy_drvdata *data;
|
|
struct phy_provider *phy_provider;
|
|
|
|
phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL);
|
|
if (!phy_dwc3)
|
|
return -ENOMEM;
|
|
|
|
data = of_device_get_match_data(&pdev->dev);
|
|
|
|
phy_dwc3->dev = &pdev->dev;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res)
|
|
return -EINVAL;
|
|
size = resource_size(res);
|
|
phy_dwc3->base = devm_ioremap(phy_dwc3->dev, res->start, size);
|
|
|
|
if (!phy_dwc3->base) {
|
|
dev_err(phy_dwc3->dev, "failed to map reg\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref");
|
|
if (IS_ERR(phy_dwc3->ref_clk)) {
|
|
dev_dbg(phy_dwc3->dev, "cannot get reference clock\n");
|
|
return PTR_ERR(phy_dwc3->ref_clk);
|
|
}
|
|
|
|
clk_set_rate(phy_dwc3->ref_clk, data->clk_rate);
|
|
|
|
phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo");
|
|
if (IS_ERR(phy_dwc3->xo_clk)) {
|
|
dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n");
|
|
phy_dwc3->xo_clk = NULL;
|
|
}
|
|
|
|
/* Parse device node to probe HSIO settings */
|
|
if (device_property_read_u32(&pdev->dev, "qcom,rx-eq",
|
|
&phy_dwc3->rx_eq))
|
|
phy_dwc3->rx_eq = SSPHY_RX_EQ_VALUE;
|
|
|
|
if (device_property_read_u32(&pdev->dev, "qcom,tx-deamp_3_5db",
|
|
&phy_dwc3->tx_deamp_3_5db))
|
|
phy_dwc3->tx_deamp_3_5db = SSPHY_TX_DEEMPH_3_5DB;
|
|
|
|
if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll))
|
|
phy_dwc3->mpll = SSPHY_MPLL_VALUE;
|
|
|
|
generic_phy = devm_phy_create(phy_dwc3->dev, pdev->dev.of_node, &data->ops);
|
|
|
|
if (IS_ERR(generic_phy))
|
|
return PTR_ERR(generic_phy);
|
|
|
|
phy_set_drvdata(generic_phy, phy_dwc3);
|
|
platform_set_drvdata(pdev, phy_dwc3);
|
|
|
|
phy_provider = devm_of_phy_provider_register(phy_dwc3->dev,
|
|
of_phy_simple_xlate);
|
|
|
|
if (IS_ERR(phy_provider))
|
|
return PTR_ERR(phy_provider);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver qcom_ipq806x_usb_phy_driver = {
|
|
.probe = qcom_ipq806x_usb_phy_probe,
|
|
.driver = {
|
|
.name = "qcom-ipq806x-usb-phy",
|
|
.of_match_table = qcom_ipq806x_usb_phy_table,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(qcom_ipq806x_usb_phy_driver);
|
|
|
|
MODULE_ALIAS("platform:phy-qcom-ipq806x-usb");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
|
|
MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
|
|
MODULE_DESCRIPTION("DesignWare USB3 QCOM PHY driver");
|