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e03d37d859
This patch is addition to the already merged commit on non-empty uart fifo read abort. "ce13d4716a276f4331d78ba28a5093a63822ab95" OMAP3630 and OMAP4430 UART IP blocks have a restriction on TX FIFO too. If you try to write to the tx fifo when it is full, the system aborts. More details on this thread are here: http://www.mail-archive.com/linux-omap@vger.kernel.org/msg19447.html This can be easily reproducible by not suppressing interconnect errors or long duration testing where continuous prints over console from multiple threads. This patch is addressing the issue by ensuring that write is not issued while fifo is full. A timeout is added to avoid any hang on fifo-full for 10 mS which is unlikely case. Patch is validated on OMAP3630 and OMAP4 SDP. V2 version removed the additional 1 uS on every TX as per Tony's suggestion Signed-off-by: Woodruff Richard <r-woodruff2@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> CC: Ghorai Sukumar <s-ghorai@ti.com> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> |
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