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https://github.com/edk2-porting/linux-next.git
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1c17ae8af9
The cxgb3 driver is incorrectly configuring the HW CQ context for CQ's that use overflow-avoidance. Namely the RDMA control CQ. This results in a bad DMA from the device to bus address 0. The solution is to set the CQ_ERR bit in the context for these types of CQs. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
256 lines
7.8 KiB
C
256 lines
7.8 KiB
C
/*
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* This file is automatically generated --- any changes will be lost.
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*/
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#ifndef _SGE_DEFS_H
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#define _SGE_DEFS_H
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#define S_EC_CREDITS 0
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#define M_EC_CREDITS 0x7FFF
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#define V_EC_CREDITS(x) ((x) << S_EC_CREDITS)
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#define G_EC_CREDITS(x) (((x) >> S_EC_CREDITS) & M_EC_CREDITS)
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#define S_EC_GTS 15
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#define V_EC_GTS(x) ((x) << S_EC_GTS)
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#define F_EC_GTS V_EC_GTS(1U)
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#define S_EC_INDEX 16
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#define M_EC_INDEX 0xFFFF
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#define V_EC_INDEX(x) ((x) << S_EC_INDEX)
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#define G_EC_INDEX(x) (((x) >> S_EC_INDEX) & M_EC_INDEX)
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#define S_EC_SIZE 0
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#define M_EC_SIZE 0xFFFF
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#define V_EC_SIZE(x) ((x) << S_EC_SIZE)
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#define G_EC_SIZE(x) (((x) >> S_EC_SIZE) & M_EC_SIZE)
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#define S_EC_BASE_LO 16
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#define M_EC_BASE_LO 0xFFFF
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#define V_EC_BASE_LO(x) ((x) << S_EC_BASE_LO)
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#define G_EC_BASE_LO(x) (((x) >> S_EC_BASE_LO) & M_EC_BASE_LO)
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#define S_EC_BASE_HI 0
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#define M_EC_BASE_HI 0xF
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#define V_EC_BASE_HI(x) ((x) << S_EC_BASE_HI)
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#define G_EC_BASE_HI(x) (((x) >> S_EC_BASE_HI) & M_EC_BASE_HI)
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#define S_EC_RESPQ 4
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#define M_EC_RESPQ 0x7
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#define V_EC_RESPQ(x) ((x) << S_EC_RESPQ)
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#define G_EC_RESPQ(x) (((x) >> S_EC_RESPQ) & M_EC_RESPQ)
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#define S_EC_TYPE 7
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#define M_EC_TYPE 0x7
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#define V_EC_TYPE(x) ((x) << S_EC_TYPE)
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#define G_EC_TYPE(x) (((x) >> S_EC_TYPE) & M_EC_TYPE)
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#define S_EC_GEN 10
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#define V_EC_GEN(x) ((x) << S_EC_GEN)
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#define F_EC_GEN V_EC_GEN(1U)
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#define S_EC_UP_TOKEN 11
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#define M_EC_UP_TOKEN 0xFFFFF
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#define V_EC_UP_TOKEN(x) ((x) << S_EC_UP_TOKEN)
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#define G_EC_UP_TOKEN(x) (((x) >> S_EC_UP_TOKEN) & M_EC_UP_TOKEN)
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#define S_EC_VALID 31
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#define V_EC_VALID(x) ((x) << S_EC_VALID)
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#define F_EC_VALID V_EC_VALID(1U)
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#define S_RQ_MSI_VEC 20
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#define M_RQ_MSI_VEC 0x3F
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#define V_RQ_MSI_VEC(x) ((x) << S_RQ_MSI_VEC)
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#define G_RQ_MSI_VEC(x) (((x) >> S_RQ_MSI_VEC) & M_RQ_MSI_VEC)
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#define S_RQ_INTR_EN 26
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#define V_RQ_INTR_EN(x) ((x) << S_RQ_INTR_EN)
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#define F_RQ_INTR_EN V_RQ_INTR_EN(1U)
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#define S_RQ_GEN 28
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#define V_RQ_GEN(x) ((x) << S_RQ_GEN)
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#define F_RQ_GEN V_RQ_GEN(1U)
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#define S_CQ_INDEX 0
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#define M_CQ_INDEX 0xFFFF
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#define V_CQ_INDEX(x) ((x) << S_CQ_INDEX)
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#define G_CQ_INDEX(x) (((x) >> S_CQ_INDEX) & M_CQ_INDEX)
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#define S_CQ_SIZE 16
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#define M_CQ_SIZE 0xFFFF
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#define V_CQ_SIZE(x) ((x) << S_CQ_SIZE)
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#define G_CQ_SIZE(x) (((x) >> S_CQ_SIZE) & M_CQ_SIZE)
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#define S_CQ_BASE_HI 0
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#define M_CQ_BASE_HI 0xFFFFF
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#define V_CQ_BASE_HI(x) ((x) << S_CQ_BASE_HI)
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#define G_CQ_BASE_HI(x) (((x) >> S_CQ_BASE_HI) & M_CQ_BASE_HI)
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#define S_CQ_RSPQ 20
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#define M_CQ_RSPQ 0x3F
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#define V_CQ_RSPQ(x) ((x) << S_CQ_RSPQ)
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#define G_CQ_RSPQ(x) (((x) >> S_CQ_RSPQ) & M_CQ_RSPQ)
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#define S_CQ_ASYNC_NOTIF 26
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#define V_CQ_ASYNC_NOTIF(x) ((x) << S_CQ_ASYNC_NOTIF)
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#define F_CQ_ASYNC_NOTIF V_CQ_ASYNC_NOTIF(1U)
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#define S_CQ_ARMED 27
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#define V_CQ_ARMED(x) ((x) << S_CQ_ARMED)
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#define F_CQ_ARMED V_CQ_ARMED(1U)
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#define S_CQ_ASYNC_NOTIF_SOL 28
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#define V_CQ_ASYNC_NOTIF_SOL(x) ((x) << S_CQ_ASYNC_NOTIF_SOL)
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#define F_CQ_ASYNC_NOTIF_SOL V_CQ_ASYNC_NOTIF_SOL(1U)
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#define S_CQ_GEN 29
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#define V_CQ_GEN(x) ((x) << S_CQ_GEN)
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#define F_CQ_GEN V_CQ_GEN(1U)
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#define S_CQ_ERR 30
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#define V_CQ_ERR(x) ((x) << S_CQ_ERR)
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#define F_CQ_ERR V_CQ_ERR(1U)
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#define S_CQ_OVERFLOW_MODE 31
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#define V_CQ_OVERFLOW_MODE(x) ((x) << S_CQ_OVERFLOW_MODE)
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#define F_CQ_OVERFLOW_MODE V_CQ_OVERFLOW_MODE(1U)
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#define S_CQ_CREDITS 0
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#define M_CQ_CREDITS 0xFFFF
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#define V_CQ_CREDITS(x) ((x) << S_CQ_CREDITS)
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#define G_CQ_CREDITS(x) (((x) >> S_CQ_CREDITS) & M_CQ_CREDITS)
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#define S_CQ_CREDIT_THRES 16
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#define M_CQ_CREDIT_THRES 0x1FFF
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#define V_CQ_CREDIT_THRES(x) ((x) << S_CQ_CREDIT_THRES)
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#define G_CQ_CREDIT_THRES(x) (((x) >> S_CQ_CREDIT_THRES) & M_CQ_CREDIT_THRES)
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#define S_FL_BASE_HI 0
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#define M_FL_BASE_HI 0xFFFFF
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#define V_FL_BASE_HI(x) ((x) << S_FL_BASE_HI)
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#define G_FL_BASE_HI(x) (((x) >> S_FL_BASE_HI) & M_FL_BASE_HI)
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#define S_FL_INDEX_LO 20
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#define M_FL_INDEX_LO 0xFFF
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#define V_FL_INDEX_LO(x) ((x) << S_FL_INDEX_LO)
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#define G_FL_INDEX_LO(x) (((x) >> S_FL_INDEX_LO) & M_FL_INDEX_LO)
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#define S_FL_INDEX_HI 0
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#define M_FL_INDEX_HI 0xF
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#define V_FL_INDEX_HI(x) ((x) << S_FL_INDEX_HI)
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#define G_FL_INDEX_HI(x) (((x) >> S_FL_INDEX_HI) & M_FL_INDEX_HI)
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#define S_FL_SIZE 4
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#define M_FL_SIZE 0xFFFF
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#define V_FL_SIZE(x) ((x) << S_FL_SIZE)
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#define G_FL_SIZE(x) (((x) >> S_FL_SIZE) & M_FL_SIZE)
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#define S_FL_GEN 20
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#define V_FL_GEN(x) ((x) << S_FL_GEN)
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#define F_FL_GEN V_FL_GEN(1U)
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#define S_FL_ENTRY_SIZE_LO 21
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#define M_FL_ENTRY_SIZE_LO 0x7FF
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#define V_FL_ENTRY_SIZE_LO(x) ((x) << S_FL_ENTRY_SIZE_LO)
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#define G_FL_ENTRY_SIZE_LO(x) (((x) >> S_FL_ENTRY_SIZE_LO) & M_FL_ENTRY_SIZE_LO)
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#define S_FL_ENTRY_SIZE_HI 0
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#define M_FL_ENTRY_SIZE_HI 0x1FFFFF
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#define V_FL_ENTRY_SIZE_HI(x) ((x) << S_FL_ENTRY_SIZE_HI)
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#define G_FL_ENTRY_SIZE_HI(x) (((x) >> S_FL_ENTRY_SIZE_HI) & M_FL_ENTRY_SIZE_HI)
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#define S_FL_CONG_THRES 21
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#define M_FL_CONG_THRES 0x3FF
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#define V_FL_CONG_THRES(x) ((x) << S_FL_CONG_THRES)
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#define G_FL_CONG_THRES(x) (((x) >> S_FL_CONG_THRES) & M_FL_CONG_THRES)
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#define S_FL_GTS 31
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#define V_FL_GTS(x) ((x) << S_FL_GTS)
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#define F_FL_GTS V_FL_GTS(1U)
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#define S_FLD_GEN1 31
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#define V_FLD_GEN1(x) ((x) << S_FLD_GEN1)
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#define F_FLD_GEN1 V_FLD_GEN1(1U)
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#define S_FLD_GEN2 0
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#define V_FLD_GEN2(x) ((x) << S_FLD_GEN2)
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#define F_FLD_GEN2 V_FLD_GEN2(1U)
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#define S_RSPD_TXQ1_CR 0
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#define M_RSPD_TXQ1_CR 0x7F
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#define V_RSPD_TXQ1_CR(x) ((x) << S_RSPD_TXQ1_CR)
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#define G_RSPD_TXQ1_CR(x) (((x) >> S_RSPD_TXQ1_CR) & M_RSPD_TXQ1_CR)
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#define S_RSPD_TXQ1_GTS 7
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#define V_RSPD_TXQ1_GTS(x) ((x) << S_RSPD_TXQ1_GTS)
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#define F_RSPD_TXQ1_GTS V_RSPD_TXQ1_GTS(1U)
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#define S_RSPD_TXQ2_CR 8
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#define M_RSPD_TXQ2_CR 0x7F
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#define V_RSPD_TXQ2_CR(x) ((x) << S_RSPD_TXQ2_CR)
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#define G_RSPD_TXQ2_CR(x) (((x) >> S_RSPD_TXQ2_CR) & M_RSPD_TXQ2_CR)
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#define S_RSPD_TXQ2_GTS 15
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#define V_RSPD_TXQ2_GTS(x) ((x) << S_RSPD_TXQ2_GTS)
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#define F_RSPD_TXQ2_GTS V_RSPD_TXQ2_GTS(1U)
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#define S_RSPD_TXQ0_CR 16
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#define M_RSPD_TXQ0_CR 0x7F
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#define V_RSPD_TXQ0_CR(x) ((x) << S_RSPD_TXQ0_CR)
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#define G_RSPD_TXQ0_CR(x) (((x) >> S_RSPD_TXQ0_CR) & M_RSPD_TXQ0_CR)
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#define S_RSPD_TXQ0_GTS 23
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#define V_RSPD_TXQ0_GTS(x) ((x) << S_RSPD_TXQ0_GTS)
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#define F_RSPD_TXQ0_GTS V_RSPD_TXQ0_GTS(1U)
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#define S_RSPD_EOP 24
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#define V_RSPD_EOP(x) ((x) << S_RSPD_EOP)
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#define F_RSPD_EOP V_RSPD_EOP(1U)
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#define S_RSPD_SOP 25
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#define V_RSPD_SOP(x) ((x) << S_RSPD_SOP)
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#define F_RSPD_SOP V_RSPD_SOP(1U)
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#define S_RSPD_ASYNC_NOTIF 26
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#define V_RSPD_ASYNC_NOTIF(x) ((x) << S_RSPD_ASYNC_NOTIF)
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#define F_RSPD_ASYNC_NOTIF V_RSPD_ASYNC_NOTIF(1U)
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#define S_RSPD_FL0_GTS 27
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#define V_RSPD_FL0_GTS(x) ((x) << S_RSPD_FL0_GTS)
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#define F_RSPD_FL0_GTS V_RSPD_FL0_GTS(1U)
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#define S_RSPD_FL1_GTS 28
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#define V_RSPD_FL1_GTS(x) ((x) << S_RSPD_FL1_GTS)
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#define F_RSPD_FL1_GTS V_RSPD_FL1_GTS(1U)
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#define S_RSPD_IMM_DATA_VALID 29
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#define V_RSPD_IMM_DATA_VALID(x) ((x) << S_RSPD_IMM_DATA_VALID)
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#define F_RSPD_IMM_DATA_VALID V_RSPD_IMM_DATA_VALID(1U)
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#define S_RSPD_OFFLOAD 30
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#define V_RSPD_OFFLOAD(x) ((x) << S_RSPD_OFFLOAD)
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#define F_RSPD_OFFLOAD V_RSPD_OFFLOAD(1U)
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#define S_RSPD_GEN1 31
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#define V_RSPD_GEN1(x) ((x) << S_RSPD_GEN1)
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#define F_RSPD_GEN1 V_RSPD_GEN1(1U)
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#define S_RSPD_LEN 0
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#define M_RSPD_LEN 0x7FFFFFFF
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#define V_RSPD_LEN(x) ((x) << S_RSPD_LEN)
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#define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN)
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#define S_RSPD_FLQ 31
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#define V_RSPD_FLQ(x) ((x) << S_RSPD_FLQ)
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#define F_RSPD_FLQ V_RSPD_FLQ(1U)
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#define S_RSPD_GEN2 0
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#define V_RSPD_GEN2(x) ((x) << S_RSPD_GEN2)
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#define F_RSPD_GEN2 V_RSPD_GEN2(1U)
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#define S_RSPD_INR_VEC 1
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#define M_RSPD_INR_VEC 0x7F
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#define V_RSPD_INR_VEC(x) ((x) << S_RSPD_INR_VEC)
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#define G_RSPD_INR_VEC(x) (((x) >> S_RSPD_INR_VEC) & M_RSPD_INR_VEC)
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#endif /* _SGE_DEFS_H */
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