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af0490810c
Convert IRDA drivers to use already existing net_device_stats structure in network device. This is a pre-cursor to conversion to net_device ops. Compile tested only. Signed-off-by: Stephen Hemminger <shemminger@vyatta.com> Signed-off-by: David S. Miller <davem@davemloft.net>
229 lines
7.6 KiB
C
229 lines
7.6 KiB
C
/*********************************************************************
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*
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* Filename: ali-ircc.h
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* Version: 0.5
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* Description: Driver for the ALI M1535D and M1543C FIR Controller
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* Status: Experimental.
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* Author: Benjamin Kong <benjamin_kong@ali.com.tw>
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* Created at: 2000/10/16 03:46PM
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* Modified at: 2001/1/3 02:56PM
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* Modified by: Benjamin Kong <benjamin_kong@ali.com.tw>
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*
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* Copyright (c) 2000 Benjamin Kong <benjamin_kong@ali.com.tw>
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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********************************************************************/
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#ifndef ALI_IRCC_H
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#define ALI_IRCC_H
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#include <linux/time.h>
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#include <linux/spinlock.h>
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#include <linux/pm.h>
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#include <linux/types.h>
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#include <asm/io.h>
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/* SIR Register */
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/* Usr definition of linux/serial_reg.h */
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/* FIR Register */
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#define BANK0 0x20
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#define BANK1 0x21
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#define BANK2 0x22
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#define BANK3 0x23
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#define FIR_MCR 0x07 /* Master Control Register */
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/* Bank 0 */
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#define FIR_DR 0x00 /* Alias 0, FIR Data Register (R/W) */
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#define FIR_IER 0x01 /* Alias 1, FIR Interrupt Enable Register (R/W) */
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#define FIR_IIR 0x02 /* Alias 2, FIR Interrupt Identification Register (Read only) */
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#define FIR_LCR_A 0x03 /* Alias 3, FIR Line Control Register A (R/W) */
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#define FIR_LCR_B 0x04 /* Alias 4, FIR Line Control Register B (R/W) */
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#define FIR_LSR 0x05 /* Alias 5, FIR Line Status Register (R/W) */
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#define FIR_BSR 0x06 /* Alias 6, FIR Bus Status Register (Read only) */
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/* Alias 1 */
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#define IER_FIFO 0x10 /* FIR FIFO Interrupt Enable */
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#define IER_TIMER 0x20 /* Timer Interrupt Enable */
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#define IER_EOM 0x40 /* End of Message Interrupt Enable */
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#define IER_ACT 0x80 /* Active Frame Interrupt Enable */
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/* Alias 2 */
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#define IIR_FIFO 0x10 /* FIR FIFO Interrupt */
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#define IIR_TIMER 0x20 /* Timer Interrupt */
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#define IIR_EOM 0x40 /* End of Message Interrupt */
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#define IIR_ACT 0x80 /* Active Frame Interrupt */
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/* Alias 3 */
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#define LCR_A_FIFO_RESET 0x80 /* FIFO Reset */
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/* Alias 4 */
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#define LCR_B_BW 0x10 /* Brick Wall */
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#define LCR_B_SIP 0x20 /* SIP Enable */
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#define LCR_B_TX_MODE 0x40 /* Transmit Mode */
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#define LCR_B_RX_MODE 0x80 /* Receive Mode */
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/* Alias 5 */
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#define LSR_FIR_LSA 0x00 /* FIR Line Status Address */
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#define LSR_FRAME_ABORT 0x08 /* Frame Abort */
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#define LSR_CRC_ERROR 0x10 /* CRC Error */
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#define LSR_SIZE_ERROR 0x20 /* Size Error */
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#define LSR_FRAME_ERROR 0x40 /* Frame Error */
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#define LSR_FIFO_UR 0x80 /* FIFO Underrun */
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#define LSR_FIFO_OR 0x80 /* FIFO Overrun */
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/* Alias 6 */
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#define BSR_FIFO_NOT_EMPTY 0x80 /* FIFO Not Empty */
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/* Bank 1 */
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#define FIR_CR 0x00 /* Alias 0, FIR Configuration Register (R/W) */
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#define FIR_FIFO_TR 0x01 /* Alias 1, FIR FIFO Threshold Register (R/W) */
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#define FIR_DMA_TR 0x02 /* Alias 2, FIR DMA Threshold Register (R/W) */
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#define FIR_TIMER_IIR 0x03 /* Alias 3, FIR Timer interrupt interval register (W/O) */
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#define FIR_FIFO_FR 0x03 /* Alias 3, FIR FIFO Flag register (R/O) */
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#define FIR_FIFO_RAR 0x04 /* Alias 4, FIR FIFO Read Address register (R/O) */
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#define FIR_FIFO_WAR 0x05 /* Alias 5, FIR FIFO Write Address register (R/O) */
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#define FIR_TR 0x06 /* Alias 6, Test REgister (W/O) */
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/* Alias 0 */
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#define CR_DMA_EN 0x01 /* DMA Enable */
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#define CR_DMA_BURST 0x02 /* DMA Burst Mode */
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#define CR_TIMER_EN 0x08 /* Timer Enable */
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/* Alias 3 */
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#define TIMER_IIR_500 0x00 /* 500 us */
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#define TIMER_IIR_1ms 0x01 /* 1 ms */
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#define TIMER_IIR_2ms 0x02 /* 2 ms */
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#define TIMER_IIR_4ms 0x03 /* 4 ms */
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/* Bank 2 */
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#define FIR_IRDA_CR 0x00 /* Alias 0, IrDA Control Register (R/W) */
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#define FIR_BOF_CR 0x01 /* Alias 1, BOF Count Register (R/W) */
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#define FIR_BW_CR 0x02 /* Alias 2, Brick Wall Count Register (R/W) */
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#define FIR_TX_DSR_HI 0x03 /* Alias 3, TX Data Size Register (high) (R/W) */
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#define FIR_TX_DSR_LO 0x04 /* Alias 4, TX Data Size Register (low) (R/W) */
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#define FIR_RX_DSR_HI 0x05 /* Alias 5, RX Data Size Register (high) (R/W) */
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#define FIR_RX_DSR_LO 0x06 /* Alias 6, RX Data Size Register (low) (R/W) */
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/* Alias 0 */
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#define IRDA_CR_HDLC1152 0x80 /* 1.152Mbps HDLC Select */
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#define IRDA_CR_CRC 0X40 /* CRC Select. */
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#define IRDA_CR_HDLC 0x20 /* HDLC select. */
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#define IRDA_CR_HP_MODE 0x10 /* HP mode (read only) */
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#define IRDA_CR_SD_ST 0x08 /* SD/MODE State. */
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#define IRDA_CR_FIR_SIN 0x04 /* FIR SIN Select. */
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#define IRDA_CR_ITTX_0 0x02 /* SOUT State. IRTX force to 0 */
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#define IRDA_CR_ITTX_1 0x03 /* SOUT State. IRTX force to 1 */
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/* Bank 3 */
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#define FIR_ID_VR 0x00 /* Alias 0, FIR ID Version Register (R/O) */
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#define FIR_MODULE_CR 0x01 /* Alias 1, FIR Module Control Register (R/W) */
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#define FIR_IO_BASE_HI 0x02 /* Alias 2, FIR Higher I/O Base Address Register (R/O) */
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#define FIR_IO_BASE_LO 0x03 /* Alias 3, FIR Lower I/O Base Address Register (R/O) */
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#define FIR_IRQ_CR 0x04 /* Alias 4, FIR IRQ Channel Register (R/O) */
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#define FIR_DMA_CR 0x05 /* Alias 5, FIR DMA Channel Register (R/O) */
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struct ali_chip {
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char *name;
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int cfg[2];
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unsigned char entr1;
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unsigned char entr2;
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unsigned char cid_index;
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unsigned char cid_value;
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int (*probe)(struct ali_chip *chip, chipio_t *info);
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int (*init)(struct ali_chip *chip, chipio_t *info);
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};
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typedef struct ali_chip ali_chip_t;
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/* DMA modes needed */
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#define DMA_TX_MODE 0x08 /* Mem to I/O, ++, demand. */
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#define DMA_RX_MODE 0x04 /* I/O to mem, ++, demand. */
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#define MAX_TX_WINDOW 7
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#define MAX_RX_WINDOW 7
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#define TX_FIFO_Threshold 8
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#define RX_FIFO_Threshold 1
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#define TX_DMA_Threshold 1
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#define RX_DMA_Threshold 1
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/* For storing entries in the status FIFO */
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struct st_fifo_entry {
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int status;
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int len;
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};
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struct st_fifo {
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struct st_fifo_entry entries[MAX_RX_WINDOW];
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int pending_bytes;
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int head;
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int tail;
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int len;
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};
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struct frame_cb {
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void *start; /* Start of frame in DMA mem */
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int len; /* Length of frame in DMA mem */
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};
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struct tx_fifo {
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struct frame_cb queue[MAX_TX_WINDOW]; /* Info about frames in queue */
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int ptr; /* Currently being sent */
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int len; /* Length of queue */
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int free; /* Next free slot */
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void *tail; /* Next free start in DMA mem */
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};
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/* Private data for each instance */
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struct ali_ircc_cb {
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struct st_fifo st_fifo; /* Info about received frames */
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struct tx_fifo tx_fifo; /* Info about frames to be transmitted */
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struct net_device *netdev; /* Yes! we are some kind of netdevice */
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struct irlap_cb *irlap; /* The link layer we are binded to */
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struct qos_info qos; /* QoS capabilities for this device */
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chipio_t io; /* IrDA controller information */
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iobuff_t tx_buff; /* Transmit buffer */
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iobuff_t rx_buff; /* Receive buffer */
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dma_addr_t tx_buff_dma;
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dma_addr_t rx_buff_dma;
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__u8 ier; /* Interrupt enable register */
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__u8 InterruptID; /* Interrupt ID */
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__u8 BusStatus; /* Bus Status */
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__u8 LineStatus; /* Line Status */
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unsigned char rcvFramesOverflow;
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struct timeval stamp;
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struct timeval now;
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spinlock_t lock; /* For serializing operations */
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__u32 new_speed;
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int index; /* Instance index */
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unsigned char fifo_opti_buf;
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};
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static inline void switch_bank(int iobase, int bank)
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{
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outb(bank, iobase+FIR_MCR);
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}
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#endif /* ALI_IRCC_H */
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